
s-link:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400570 <_init>:
  400570:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400574:	910003fd 	mov	x29, sp
  400578:	94000040 	bl	400678 <call_weak_fn>
  40057c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400580:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400590 <.plt>:
  400590:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400594:	d0000090 	adrp	x16, 412000 <__FRAME_END__+0xfad4>
  400598:	f947fe11 	ldr	x17, [x16, #4088]
  40059c:	913fe210 	add	x16, x16, #0xff8
  4005a0:	d61f0220 	br	x17
  4005a4:	d503201f 	nop
  4005a8:	d503201f 	nop
  4005ac:	d503201f 	nop

00000000004005b0 <malloc@plt>:
  4005b0:	f0000090 	adrp	x16, 413000 <malloc@GLIBC_2.17>
  4005b4:	f9400211 	ldr	x17, [x16]
  4005b8:	91000210 	add	x16, x16, #0x0
  4005bc:	d61f0220 	br	x17

00000000004005c0 <__libc_start_main@plt>:
  4005c0:	f0000090 	adrp	x16, 413000 <malloc@GLIBC_2.17>
  4005c4:	f9400611 	ldr	x17, [x16, #8]
  4005c8:	91002210 	add	x16, x16, #0x8
  4005cc:	d61f0220 	br	x17

00000000004005d0 <__gmon_start__@plt>:
  4005d0:	f0000090 	adrp	x16, 413000 <malloc@GLIBC_2.17>
  4005d4:	f9400a11 	ldr	x17, [x16, #16]
  4005d8:	91004210 	add	x16, x16, #0x10
  4005dc:	d61f0220 	br	x17

00000000004005e0 <abort@plt>:
  4005e0:	f0000090 	adrp	x16, 413000 <malloc@GLIBC_2.17>
  4005e4:	f9400e11 	ldr	x17, [x16, #24]
  4005e8:	91006210 	add	x16, x16, #0x18
  4005ec:	d61f0220 	br	x17

00000000004005f0 <puts@plt>:
  4005f0:	f0000090 	adrp	x16, 413000 <malloc@GLIBC_2.17>
  4005f4:	f9401211 	ldr	x17, [x16, #32]
  4005f8:	91008210 	add	x16, x16, #0x20
  4005fc:	d61f0220 	br	x17

0000000000400600 <free@plt>:
  400600:	f0000090 	adrp	x16, 413000 <malloc@GLIBC_2.17>
  400604:	f9401611 	ldr	x17, [x16, #40]
  400608:	9100a210 	add	x16, x16, #0x28
  40060c:	d61f0220 	br	x17

0000000000400610 <printf@plt>:
  400610:	f0000090 	adrp	x16, 413000 <malloc@GLIBC_2.17>
  400614:	f9401a11 	ldr	x17, [x16, #48]
  400618:	9100c210 	add	x16, x16, #0x30
  40061c:	d61f0220 	br	x17

0000000000400620 <putchar@plt>:
  400620:	f0000090 	adrp	x16, 413000 <malloc@GLIBC_2.17>
  400624:	f9401e11 	ldr	x17, [x16, #56]
  400628:	9100e210 	add	x16, x16, #0x38
  40062c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400630 <_start>:
  400630:	d280001d 	mov	x29, #0x0                   	// #0
  400634:	d280001e 	mov	x30, #0x0                   	// #0
  400638:	aa0003e5 	mov	x5, x0
  40063c:	f94003e1 	ldr	x1, [sp]
  400640:	910023e2 	add	x2, sp, #0x8
  400644:	910003e6 	mov	x6, sp
  400648:	580000c0 	ldr	x0, 400660 <_start+0x30>
  40064c:	580000e3 	ldr	x3, 400668 <_start+0x38>
  400650:	58000104 	ldr	x4, 400670 <_start+0x40>
  400654:	97ffffdb 	bl	4005c0 <__libc_start_main@plt>
  400658:	97ffffe2 	bl	4005e0 <abort@plt>
  40065c:	00000000 	.inst	0x00000000 ; undefined
  400660:	00401d5c 	.word	0x00401d5c
  400664:	00000000 	.word	0x00000000
  400668:	00401e48 	.word	0x00401e48
  40066c:	00000000 	.word	0x00000000
  400670:	00401ec8 	.word	0x00401ec8
  400674:	00000000 	.word	0x00000000

0000000000400678 <call_weak_fn>:
  400678:	d0000080 	adrp	x0, 412000 <__FRAME_END__+0xfad4>
  40067c:	f947f000 	ldr	x0, [x0, #4064]
  400680:	b4000040 	cbz	x0, 400688 <call_weak_fn+0x10>
  400684:	17ffffd3 	b	4005d0 <__gmon_start__@plt>
  400688:	d65f03c0 	ret
  40068c:	00000000 	.inst	0x00000000 ; undefined

0000000000400690 <deregister_tm_clones>:
  400690:	f0000080 	adrp	x0, 413000 <malloc@GLIBC_2.17>
  400694:	91014000 	add	x0, x0, #0x50
  400698:	f0000081 	adrp	x1, 413000 <malloc@GLIBC_2.17>
  40069c:	91014021 	add	x1, x1, #0x50
  4006a0:	eb00003f 	cmp	x1, x0
  4006a4:	540000a0 	b.eq	4006b8 <deregister_tm_clones+0x28>  // b.none
  4006a8:	b0000001 	adrp	x1, 401000 <merge_debug+0x70>
  4006ac:	f9477421 	ldr	x1, [x1, #3816]
  4006b0:	b4000041 	cbz	x1, 4006b8 <deregister_tm_clones+0x28>
  4006b4:	d61f0020 	br	x1
  4006b8:	d65f03c0 	ret
  4006bc:	d503201f 	nop

00000000004006c0 <register_tm_clones>:
  4006c0:	f0000080 	adrp	x0, 413000 <malloc@GLIBC_2.17>
  4006c4:	91014000 	add	x0, x0, #0x50
  4006c8:	f0000081 	adrp	x1, 413000 <malloc@GLIBC_2.17>
  4006cc:	91014021 	add	x1, x1, #0x50
  4006d0:	cb000021 	sub	x1, x1, x0
  4006d4:	9343fc21 	asr	x1, x1, #3
  4006d8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4006dc:	9341fc21 	asr	x1, x1, #1
  4006e0:	b40000a1 	cbz	x1, 4006f4 <register_tm_clones+0x34>
  4006e4:	b0000002 	adrp	x2, 401000 <merge_debug+0x70>
  4006e8:	f9477842 	ldr	x2, [x2, #3824]
  4006ec:	b4000042 	cbz	x2, 4006f4 <register_tm_clones+0x34>
  4006f0:	d61f0040 	br	x2
  4006f4:	d65f03c0 	ret

00000000004006f8 <__do_global_dtors_aux>:
  4006f8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4006fc:	910003fd 	mov	x29, sp
  400700:	f9000bf3 	str	x19, [sp, #16]
  400704:	f0000093 	adrp	x19, 413000 <malloc@GLIBC_2.17>
  400708:	39414260 	ldrb	w0, [x19, #80]
  40070c:	35000080 	cbnz	w0, 40071c <__do_global_dtors_aux+0x24>
  400710:	97ffffe0 	bl	400690 <deregister_tm_clones>
  400714:	52800020 	mov	w0, #0x1                   	// #1
  400718:	39014260 	strb	w0, [x19, #80]
  40071c:	f9400bf3 	ldr	x19, [sp, #16]
  400720:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400724:	d65f03c0 	ret

0000000000400728 <frame_dummy>:
  400728:	17ffffe6 	b	4006c0 <register_tm_clones>

000000000040072c <display_debug>:
  40072c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400730:	910003fd 	mov	x29, sp
  400734:	f9000fa0 	str	x0, [x29, #24]
  400738:	f9400fa0 	ldr	x0, [x29, #24]
  40073c:	f9400000 	ldr	x0, [x0]
  400740:	f90017a0 	str	x0, [x29, #40]
  400744:	1400000b 	b	400770 <display_debug+0x44>
  400748:	f94017a0 	ldr	x0, [x29, #40]
  40074c:	b9400001 	ldr	w1, [x0]
  400750:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  400754:	913be000 	add	x0, x0, #0xef8
  400758:	2a0103e2 	mov	w2, w1
  40075c:	f94017a1 	ldr	x1, [x29, #40]
  400760:	97ffffac 	bl	400610 <printf@plt>
  400764:	f94017a0 	ldr	x0, [x29, #40]
  400768:	f9400400 	ldr	x0, [x0, #8]
  40076c:	f90017a0 	str	x0, [x29, #40]
  400770:	f94017a0 	ldr	x0, [x29, #40]
  400774:	f100001f 	cmp	x0, #0x0
  400778:	54fffe81 	b.ne	400748 <display_debug+0x1c>  // b.any
  40077c:	52800140 	mov	w0, #0xa                   	// #10
  400780:	97ffffa8 	bl	400620 <putchar@plt>
  400784:	d503201f 	nop
  400788:	a8c37bfd 	ldp	x29, x30, [sp], #48
  40078c:	d65f03c0 	ret

0000000000400790 <reverse_perfect_debug>:
  400790:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400794:	910003fd 	mov	x29, sp
  400798:	f9000fa0 	str	x0, [x29, #24]
  40079c:	f9400fa0 	ldr	x0, [x29, #24]
  4007a0:	f9400401 	ldr	x1, [x0, #8]
  4007a4:	f9400fa0 	ldr	x0, [x29, #24]
  4007a8:	f9400400 	ldr	x0, [x0, #8]
  4007ac:	f9400402 	ldr	x2, [x0, #8]
  4007b0:	f9400fa0 	ldr	x0, [x29, #24]
  4007b4:	f9400400 	ldr	x0, [x0, #8]
  4007b8:	f9400400 	ldr	x0, [x0, #8]
  4007bc:	f9400403 	ldr	x3, [x0, #8]
  4007c0:	f9400fa0 	ldr	x0, [x29, #24]
  4007c4:	f9400400 	ldr	x0, [x0, #8]
  4007c8:	f9400400 	ldr	x0, [x0, #8]
  4007cc:	f9400400 	ldr	x0, [x0, #8]
  4007d0:	f9400404 	ldr	x4, [x0, #8]
  4007d4:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  4007d8:	913c2000 	add	x0, x0, #0xf08
  4007dc:	aa0403e5 	mov	x5, x4
  4007e0:	aa0303e4 	mov	x4, x3
  4007e4:	aa0203e3 	mov	x3, x2
  4007e8:	aa0103e2 	mov	x2, x1
  4007ec:	f9400fa1 	ldr	x1, [x29, #24]
  4007f0:	97ffff88 	bl	400610 <printf@plt>
  4007f4:	f9400fa0 	ldr	x0, [x29, #24]
  4007f8:	f90017a0 	str	x0, [x29, #40]
  4007fc:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  400800:	913c6000 	add	x0, x0, #0xf18
  400804:	f9400fa2 	ldr	x2, [x29, #24]
  400808:	f94017a1 	ldr	x1, [x29, #40]
  40080c:	97ffff81 	bl	400610 <printf@plt>
  400810:	f9000fbf 	str	xzr, [x29, #24]
  400814:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  400818:	913cc000 	add	x0, x0, #0xf30
  40081c:	f9400fa1 	ldr	x1, [x29, #24]
  400820:	97ffff7c 	bl	400610 <printf@plt>
  400824:	14000020 	b	4008a4 <reverse_perfect_debug+0x114>
  400828:	f94017a0 	ldr	x0, [x29, #40]
  40082c:	f90013a0 	str	x0, [x29, #32]
  400830:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  400834:	913d0000 	add	x0, x0, #0xf40
  400838:	f94017a2 	ldr	x2, [x29, #40]
  40083c:	f94013a1 	ldr	x1, [x29, #32]
  400840:	97ffff74 	bl	400610 <printf@plt>
  400844:	f94017a0 	ldr	x0, [x29, #40]
  400848:	f9400400 	ldr	x0, [x0, #8]
  40084c:	f90017a0 	str	x0, [x29, #40]
  400850:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  400854:	913d4000 	add	x0, x0, #0xf50
  400858:	f94017a2 	ldr	x2, [x29, #40]
  40085c:	f94017a1 	ldr	x1, [x29, #40]
  400860:	97ffff6c 	bl	400610 <printf@plt>
  400864:	f94013a0 	ldr	x0, [x29, #32]
  400868:	f9400fa1 	ldr	x1, [x29, #24]
  40086c:	f9000401 	str	x1, [x0, #8]
  400870:	f94013a0 	ldr	x0, [x29, #32]
  400874:	f9400401 	ldr	x1, [x0, #8]
  400878:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  40087c:	913da000 	add	x0, x0, #0xf68
  400880:	f9400fa2 	ldr	x2, [x29, #24]
  400884:	97ffff63 	bl	400610 <printf@plt>
  400888:	f94013a0 	ldr	x0, [x29, #32]
  40088c:	f9000fa0 	str	x0, [x29, #24]
  400890:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  400894:	913e0000 	add	x0, x0, #0xf80
  400898:	f94013a2 	ldr	x2, [x29, #32]
  40089c:	f9400fa1 	ldr	x1, [x29, #24]
  4008a0:	97ffff5c 	bl	400610 <printf@plt>
  4008a4:	f94017a0 	ldr	x0, [x29, #40]
  4008a8:	f100001f 	cmp	x0, #0x0
  4008ac:	54fffbe1 	b.ne	400828 <reverse_perfect_debug+0x98>  // b.any
  4008b0:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  4008b4:	913e6000 	add	x0, x0, #0xf98
  4008b8:	f9400fa1 	ldr	x1, [x29, #24]
  4008bc:	97ffff55 	bl	400610 <printf@plt>
  4008c0:	f9400fa0 	ldr	x0, [x29, #24]
  4008c4:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4008c8:	d65f03c0 	ret

00000000004008cc <reverse_perfect_noreturn_debug>:
  4008cc:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4008d0:	910003fd 	mov	x29, sp
  4008d4:	f9000fa0 	str	x0, [x29, #24]
  4008d8:	f9400fa0 	ldr	x0, [x29, #24]
  4008dc:	f9400002 	ldr	x2, [x0]
  4008e0:	f9400fa0 	ldr	x0, [x29, #24]
  4008e4:	f9400000 	ldr	x0, [x0]
  4008e8:	b0000001 	adrp	x1, 401000 <merge_debug+0x70>
  4008ec:	913ec025 	add	x5, x1, #0xfb0
  4008f0:	a9401003 	ldp	x3, x4, [x0]
  4008f4:	f9400fa1 	ldr	x1, [x29, #24]
  4008f8:	aa0503e0 	mov	x0, x5
  4008fc:	97ffff45 	bl	400610 <printf@plt>
  400900:	f9400fa0 	ldr	x0, [x29, #24]
  400904:	f9400000 	ldr	x0, [x0]
  400908:	f90017a0 	str	x0, [x29, #40]
  40090c:	f9400fa0 	ldr	x0, [x29, #24]
  400910:	f9400001 	ldr	x1, [x0]
  400914:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  400918:	913c6000 	add	x0, x0, #0xf18
  40091c:	aa0103e2 	mov	x2, x1
  400920:	f94017a1 	ldr	x1, [x29, #40]
  400924:	97ffff3b 	bl	400610 <printf@plt>
  400928:	f9400fa0 	ldr	x0, [x29, #24]
  40092c:	f900001f 	str	xzr, [x0]
  400930:	f9400fa0 	ldr	x0, [x29, #24]
  400934:	f9400001 	ldr	x1, [x0]
  400938:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  40093c:	913cc000 	add	x0, x0, #0xf30
  400940:	97ffff34 	bl	400610 <printf@plt>
  400944:	14000024 	b	4009d4 <reverse_perfect_noreturn_debug+0x108>
  400948:	f94017a0 	ldr	x0, [x29, #40]
  40094c:	f90013a0 	str	x0, [x29, #32]
  400950:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  400954:	913d0000 	add	x0, x0, #0xf40
  400958:	f94017a2 	ldr	x2, [x29, #40]
  40095c:	f94013a1 	ldr	x1, [x29, #32]
  400960:	97ffff2c 	bl	400610 <printf@plt>
  400964:	f94017a0 	ldr	x0, [x29, #40]
  400968:	f9400400 	ldr	x0, [x0, #8]
  40096c:	f90017a0 	str	x0, [x29, #40]
  400970:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  400974:	913d4000 	add	x0, x0, #0xf50
  400978:	f94017a2 	ldr	x2, [x29, #40]
  40097c:	f94017a1 	ldr	x1, [x29, #40]
  400980:	97ffff24 	bl	400610 <printf@plt>
  400984:	f9400fa0 	ldr	x0, [x29, #24]
  400988:	f9400001 	ldr	x1, [x0]
  40098c:	f94013a0 	ldr	x0, [x29, #32]
  400990:	f9000401 	str	x1, [x0, #8]
  400994:	f94013a0 	ldr	x0, [x29, #32]
  400998:	f9400401 	ldr	x1, [x0, #8]
  40099c:	f9400fa0 	ldr	x0, [x29, #24]
  4009a0:	f9400002 	ldr	x2, [x0]
  4009a4:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  4009a8:	913da000 	add	x0, x0, #0xf68
  4009ac:	97ffff19 	bl	400610 <printf@plt>
  4009b0:	f9400fa0 	ldr	x0, [x29, #24]
  4009b4:	f94013a1 	ldr	x1, [x29, #32]
  4009b8:	f9000001 	str	x1, [x0]
  4009bc:	f9400fa0 	ldr	x0, [x29, #24]
  4009c0:	f9400001 	ldr	x1, [x0]
  4009c4:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  4009c8:	913e0000 	add	x0, x0, #0xf80
  4009cc:	f94013a2 	ldr	x2, [x29, #32]
  4009d0:	97ffff10 	bl	400610 <printf@plt>
  4009d4:	f94017a0 	ldr	x0, [x29, #40]
  4009d8:	f100001f 	cmp	x0, #0x0
  4009dc:	54fffb61 	b.ne	400948 <reverse_perfect_noreturn_debug+0x7c>  // b.any
  4009e0:	f9400fa0 	ldr	x0, [x29, #24]
  4009e4:	f9400001 	ldr	x1, [x0]
  4009e8:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  4009ec:	913f0000 	add	x0, x0, #0xfc0
  4009f0:	97ffff08 	bl	400610 <printf@plt>
  4009f4:	d503201f 	nop
  4009f8:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4009fc:	d65f03c0 	ret

0000000000400a00 <reverse_debug>:
  400a00:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400a04:	910003fd 	mov	x29, sp
  400a08:	f9000fa0 	str	x0, [x29, #24]
  400a0c:	f9400fa0 	ldr	x0, [x29, #24]
  400a10:	f9001ba0 	str	x0, [x29, #48]
  400a14:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  400a18:	913fa000 	add	x0, x0, #0xfe8
  400a1c:	f9400fa1 	ldr	x1, [x29, #24]
  400a20:	97fffefc 	bl	400610 <printf@plt>
  400a24:	14000008 	b	400a44 <reverse_debug+0x44>
  400a28:	b0000000 	adrp	x0, 401000 <merge_debug+0x70>
  400a2c:	913fe000 	add	x0, x0, #0xff8
  400a30:	f9401ba1 	ldr	x1, [x29, #48]
  400a34:	97fffef7 	bl	400610 <printf@plt>
  400a38:	f9401ba0 	ldr	x0, [x29, #48]
  400a3c:	f9400400 	ldr	x0, [x0, #8]
  400a40:	f9001ba0 	str	x0, [x29, #48]
  400a44:	f9401ba0 	ldr	x0, [x29, #48]
  400a48:	f100001f 	cmp	x0, #0x0
  400a4c:	54fffee1 	b.ne	400a28 <reverse_debug+0x28>  // b.any
  400a50:	52800140 	mov	w0, #0xa                   	// #10
  400a54:	97fffef3 	bl	400620 <putchar@plt>
  400a58:	f9400fa0 	ldr	x0, [x29, #24]
  400a5c:	f9400401 	ldr	x1, [x0, #8]
  400a60:	f9400fa0 	ldr	x0, [x29, #24]
  400a64:	f9400400 	ldr	x0, [x0, #8]
  400a68:	f9400402 	ldr	x2, [x0, #8]
  400a6c:	f9400fa0 	ldr	x0, [x29, #24]
  400a70:	f9400400 	ldr	x0, [x0, #8]
  400a74:	f9400400 	ldr	x0, [x0, #8]
  400a78:	f9400403 	ldr	x3, [x0, #8]
  400a7c:	f9400fa0 	ldr	x0, [x29, #24]
  400a80:	f9400400 	ldr	x0, [x0, #8]
  400a84:	f9400400 	ldr	x0, [x0, #8]
  400a88:	f9400400 	ldr	x0, [x0, #8]
  400a8c:	f9400404 	ldr	x4, [x0, #8]
  400a90:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400a94:	91002000 	add	x0, x0, #0x8
  400a98:	aa0403e5 	mov	x5, x4
  400a9c:	aa0303e4 	mov	x4, x3
  400aa0:	aa0203e3 	mov	x3, x2
  400aa4:	aa0103e2 	mov	x2, x1
  400aa8:	f9400fa1 	ldr	x1, [x29, #24]
  400aac:	97fffed9 	bl	400610 <printf@plt>
  400ab0:	f9400fa0 	ldr	x0, [x29, #24]
  400ab4:	b9400001 	ldr	w1, [x0]
  400ab8:	f9400fa0 	ldr	x0, [x29, #24]
  400abc:	f9400400 	ldr	x0, [x0, #8]
  400ac0:	b9400002 	ldr	w2, [x0]
  400ac4:	f9400fa0 	ldr	x0, [x29, #24]
  400ac8:	f9400400 	ldr	x0, [x0, #8]
  400acc:	f9400400 	ldr	x0, [x0, #8]
  400ad0:	b9400003 	ldr	w3, [x0]
  400ad4:	f9400fa0 	ldr	x0, [x29, #24]
  400ad8:	f9400400 	ldr	x0, [x0, #8]
  400adc:	f9400400 	ldr	x0, [x0, #8]
  400ae0:	f9400400 	ldr	x0, [x0, #8]
  400ae4:	b9400004 	ldr	w4, [x0]
  400ae8:	f9400fa0 	ldr	x0, [x29, #24]
  400aec:	f9400400 	ldr	x0, [x0, #8]
  400af0:	f9400400 	ldr	x0, [x0, #8]
  400af4:	f9400400 	ldr	x0, [x0, #8]
  400af8:	f9400400 	ldr	x0, [x0, #8]
  400afc:	b9400005 	ldr	w5, [x0]
  400b00:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400b04:	91008000 	add	x0, x0, #0x20
  400b08:	97fffec2 	bl	400610 <printf@plt>
  400b0c:	f9400fa0 	ldr	x0, [x29, #24]
  400b10:	f9400400 	ldr	x0, [x0, #8]
  400b14:	f9001fa0 	str	x0, [x29, #56]
  400b18:	f9401fa0 	ldr	x0, [x29, #56]
  400b1c:	b9400001 	ldr	w1, [x0]
  400b20:	f9400fa0 	ldr	x0, [x29, #24]
  400b24:	f9400402 	ldr	x2, [x0, #8]
  400b28:	f9400fa0 	ldr	x0, [x29, #24]
  400b2c:	f9400400 	ldr	x0, [x0, #8]
  400b30:	b9400003 	ldr	w3, [x0]
  400b34:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400b38:	9100e000 	add	x0, x0, #0x38
  400b3c:	2a0303e4 	mov	w4, w3
  400b40:	aa0203e3 	mov	x3, x2
  400b44:	2a0103e2 	mov	w2, w1
  400b48:	f9401fa1 	ldr	x1, [x29, #56]
  400b4c:	97fffeb1 	bl	400610 <printf@plt>
  400b50:	f9400fa0 	ldr	x0, [x29, #24]
  400b54:	f900041f 	str	xzr, [x0, #8]
  400b58:	f9400fa0 	ldr	x0, [x29, #24]
  400b5c:	f9400401 	ldr	x1, [x0, #8]
  400b60:	f9400fa0 	ldr	x0, [x29, #24]
  400b64:	b9400002 	ldr	w2, [x0]
  400b68:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400b6c:	91018000 	add	x0, x0, #0x60
  400b70:	97fffea8 	bl	400610 <printf@plt>
  400b74:	1400004b 	b	400ca0 <reverse_debug+0x2a0>
  400b78:	f9401fa0 	ldr	x0, [x29, #56]
  400b7c:	b9400001 	ldr	w1, [x0]
  400b80:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400b84:	91020000 	add	x0, x0, #0x80
  400b88:	2a0103e2 	mov	w2, w1
  400b8c:	f9401fa1 	ldr	x1, [x29, #56]
  400b90:	97fffea0 	bl	400610 <printf@plt>
  400b94:	f9401fa0 	ldr	x0, [x29, #56]
  400b98:	f90017a0 	str	x0, [x29, #40]
  400b9c:	f94017a0 	ldr	x0, [x29, #40]
  400ba0:	b9400001 	ldr	w1, [x0]
  400ba4:	f9401fa0 	ldr	x0, [x29, #56]
  400ba8:	b9400002 	ldr	w2, [x0]
  400bac:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400bb0:	91026000 	add	x0, x0, #0x98
  400bb4:	2a0203e4 	mov	w4, w2
  400bb8:	f9401fa3 	ldr	x3, [x29, #56]
  400bbc:	2a0103e2 	mov	w2, w1
  400bc0:	f94017a1 	ldr	x1, [x29, #40]
  400bc4:	97fffe93 	bl	400610 <printf@plt>
  400bc8:	f9401fa0 	ldr	x0, [x29, #56]
  400bcc:	f9400400 	ldr	x0, [x0, #8]
  400bd0:	f9001fa0 	str	x0, [x29, #56]
  400bd4:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400bd8:	91030000 	add	x0, x0, #0xc0
  400bdc:	f9401fa1 	ldr	x1, [x29, #56]
  400be0:	97fffe8c 	bl	400610 <printf@plt>
  400be4:	f9401fa0 	ldr	x0, [x29, #56]
  400be8:	f100001f 	cmp	x0, #0x0
  400bec:	540000e0 	b.eq	400c08 <reverse_debug+0x208>  // b.none
  400bf0:	f9401fa0 	ldr	x0, [x29, #56]
  400bf4:	b9400001 	ldr	w1, [x0]
  400bf8:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400bfc:	91036000 	add	x0, x0, #0xd8
  400c00:	97fffe84 	bl	400610 <printf@plt>
  400c04:	14000004 	b	400c14 <reverse_debug+0x214>
  400c08:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400c0c:	91038000 	add	x0, x0, #0xe0
  400c10:	97fffe78 	bl	4005f0 <puts@plt>
  400c14:	f9400fa0 	ldr	x0, [x29, #24]
  400c18:	f9400401 	ldr	x1, [x0, #8]
  400c1c:	f94017a0 	ldr	x0, [x29, #40]
  400c20:	f9000401 	str	x1, [x0, #8]
  400c24:	f94017a0 	ldr	x0, [x29, #40]
  400c28:	f9400401 	ldr	x1, [x0, #8]
  400c2c:	f94017a0 	ldr	x0, [x29, #40]
  400c30:	b9400002 	ldr	w2, [x0]
  400c34:	f9400fa0 	ldr	x0, [x29, #24]
  400c38:	f9400403 	ldr	x3, [x0, #8]
  400c3c:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400c40:	9103a000 	add	x0, x0, #0xe8
  400c44:	97fffe73 	bl	400610 <printf@plt>
  400c48:	f9400fa0 	ldr	x0, [x29, #24]
  400c4c:	f94017a1 	ldr	x1, [x29, #40]
  400c50:	f9000401 	str	x1, [x0, #8]
  400c54:	f9400fa0 	ldr	x0, [x29, #24]
  400c58:	f9400401 	ldr	x1, [x0, #8]
  400c5c:	f9400fa0 	ldr	x0, [x29, #24]
  400c60:	f9400400 	ldr	x0, [x0, #8]
  400c64:	b9400002 	ldr	w2, [x0]
  400c68:	f94017a0 	ldr	x0, [x29, #40]
  400c6c:	b9400003 	ldr	w3, [x0]
  400c70:	f94017a0 	ldr	x0, [x29, #40]
  400c74:	f9400404 	ldr	x4, [x0, #8]
  400c78:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400c7c:	91044000 	add	x0, x0, #0x110
  400c80:	aa0403e5 	mov	x5, x4
  400c84:	2a0303e4 	mov	w4, w3
  400c88:	f94017a3 	ldr	x3, [x29, #40]
  400c8c:	97fffe61 	bl	400610 <printf@plt>
  400c90:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400c94:	9104e000 	add	x0, x0, #0x138
  400c98:	f9400fa1 	ldr	x1, [x29, #24]
  400c9c:	97fffe5d 	bl	400610 <printf@plt>
  400ca0:	f9401fa0 	ldr	x0, [x29, #56]
  400ca4:	f100001f 	cmp	x0, #0x0
  400ca8:	54fff681 	b.ne	400b78 <reverse_debug+0x178>  // b.any
  400cac:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400cb0:	91056000 	add	x0, x0, #0x158
  400cb4:	f9400fa1 	ldr	x1, [x29, #24]
  400cb8:	97fffe56 	bl	400610 <printf@plt>
  400cbc:	f9400fa0 	ldr	x0, [x29, #24]
  400cc0:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400cc4:	d65f03c0 	ret

0000000000400cc8 <reverse_1>:
  400cc8:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400ccc:	910003fd 	mov	x29, sp
  400cd0:	f9000fa0 	str	x0, [x29, #24]
  400cd4:	f9400fa0 	ldr	x0, [x29, #24]
  400cd8:	f9400401 	ldr	x1, [x0, #8]
  400cdc:	f9400fa0 	ldr	x0, [x29, #24]
  400ce0:	f9400400 	ldr	x0, [x0, #8]
  400ce4:	f9400402 	ldr	x2, [x0, #8]
  400ce8:	f9400fa0 	ldr	x0, [x29, #24]
  400cec:	f9400400 	ldr	x0, [x0, #8]
  400cf0:	f9400400 	ldr	x0, [x0, #8]
  400cf4:	f9400403 	ldr	x3, [x0, #8]
  400cf8:	f9400fa0 	ldr	x0, [x29, #24]
  400cfc:	f9400400 	ldr	x0, [x0, #8]
  400d00:	f9400400 	ldr	x0, [x0, #8]
  400d04:	f9400400 	ldr	x0, [x0, #8]
  400d08:	f9400404 	ldr	x4, [x0, #8]
  400d0c:	f9400fa0 	ldr	x0, [x29, #24]
  400d10:	f9400400 	ldr	x0, [x0, #8]
  400d14:	f9400400 	ldr	x0, [x0, #8]
  400d18:	f9400400 	ldr	x0, [x0, #8]
  400d1c:	f9400400 	ldr	x0, [x0, #8]
  400d20:	f9400405 	ldr	x5, [x0, #8]
  400d24:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400d28:	9105c000 	add	x0, x0, #0x170
  400d2c:	aa0503e6 	mov	x6, x5
  400d30:	aa0403e5 	mov	x5, x4
  400d34:	aa0303e4 	mov	x4, x3
  400d38:	aa0203e3 	mov	x3, x2
  400d3c:	aa0103e2 	mov	x2, x1
  400d40:	f9400fa1 	ldr	x1, [x29, #24]
  400d44:	97fffe33 	bl	400610 <printf@plt>
  400d48:	f9400fa0 	ldr	x0, [x29, #24]
  400d4c:	f9400400 	ldr	x0, [x0, #8]
  400d50:	f90017a0 	str	x0, [x29, #40]
  400d54:	f9400fa0 	ldr	x0, [x29, #24]
  400d58:	f9400401 	ldr	x1, [x0, #8]
  400d5c:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400d60:	91062000 	add	x0, x0, #0x188
  400d64:	aa0103e2 	mov	x2, x1
  400d68:	f94017a1 	ldr	x1, [x29, #40]
  400d6c:	97fffe29 	bl	400610 <printf@plt>
  400d70:	1400002a 	b	400e18 <reverse_1+0x150>
  400d74:	f94017a0 	ldr	x0, [x29, #40]
  400d78:	f9400400 	ldr	x0, [x0, #8]
  400d7c:	f90013a0 	str	x0, [x29, #32]
  400d80:	f94017a0 	ldr	x0, [x29, #40]
  400d84:	f9400401 	ldr	x1, [x0, #8]
  400d88:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400d8c:	9106a000 	add	x0, x0, #0x1a8
  400d90:	aa0103e2 	mov	x2, x1
  400d94:	f94013a1 	ldr	x1, [x29, #32]
  400d98:	97fffe1e 	bl	400610 <printf@plt>
  400d9c:	f94013a0 	ldr	x0, [x29, #32]
  400da0:	f9400401 	ldr	x1, [x0, #8]
  400da4:	f94017a0 	ldr	x0, [x29, #40]
  400da8:	f9000401 	str	x1, [x0, #8]
  400dac:	f94017a0 	ldr	x0, [x29, #40]
  400db0:	f9400401 	ldr	x1, [x0, #8]
  400db4:	f94013a0 	ldr	x0, [x29, #32]
  400db8:	f9400402 	ldr	x2, [x0, #8]
  400dbc:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400dc0:	91070000 	add	x0, x0, #0x1c0
  400dc4:	97fffe13 	bl	400610 <printf@plt>
  400dc8:	f9400fa0 	ldr	x0, [x29, #24]
  400dcc:	f9400401 	ldr	x1, [x0, #8]
  400dd0:	f94013a0 	ldr	x0, [x29, #32]
  400dd4:	f9000401 	str	x1, [x0, #8]
  400dd8:	f94013a0 	ldr	x0, [x29, #32]
  400ddc:	f9400401 	ldr	x1, [x0, #8]
  400de0:	f9400fa0 	ldr	x0, [x29, #24]
  400de4:	f9400402 	ldr	x2, [x0, #8]
  400de8:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400dec:	91078000 	add	x0, x0, #0x1e0
  400df0:	97fffe08 	bl	400610 <printf@plt>
  400df4:	f9400fa0 	ldr	x0, [x29, #24]
  400df8:	f94013a1 	ldr	x1, [x29, #32]
  400dfc:	f9000401 	str	x1, [x0, #8]
  400e00:	f9400fa0 	ldr	x0, [x29, #24]
  400e04:	f9400401 	ldr	x1, [x0, #8]
  400e08:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400e0c:	91080000 	add	x0, x0, #0x200
  400e10:	f94013a2 	ldr	x2, [x29, #32]
  400e14:	97fffdff 	bl	400610 <printf@plt>
  400e18:	f94017a0 	ldr	x0, [x29, #40]
  400e1c:	f9400400 	ldr	x0, [x0, #8]
  400e20:	f100001f 	cmp	x0, #0x0
  400e24:	54fffa81 	b.ne	400d74 <reverse_1+0xac>  // b.any
  400e28:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400e2c:	91088000 	add	x0, x0, #0x220
  400e30:	f9400fa1 	ldr	x1, [x29, #24]
  400e34:	97fffdf7 	bl	400610 <printf@plt>
  400e38:	f9400fa0 	ldr	x0, [x29, #24]
  400e3c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400e40:	d65f03c0 	ret

0000000000400e44 <reverse_2>:
  400e44:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400e48:	910003fd 	mov	x29, sp
  400e4c:	f9000fa0 	str	x0, [x29, #24]
  400e50:	f9400fa0 	ldr	x0, [x29, #24]
  400e54:	f9400400 	ldr	x0, [x0, #8]
  400e58:	f9001fa0 	str	x0, [x29, #56]
  400e5c:	f9400fa0 	ldr	x0, [x29, #24]
  400e60:	f9400401 	ldr	x1, [x0, #8]
  400e64:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400e68:	91090000 	add	x0, x0, #0x240
  400e6c:	aa0103e2 	mov	x2, x1
  400e70:	f9401fa1 	ldr	x1, [x29, #56]
  400e74:	97fffde7 	bl	400610 <printf@plt>
  400e78:	f9401fa0 	ldr	x0, [x29, #56]
  400e7c:	f9400400 	ldr	x0, [x0, #8]
  400e80:	f9001ba0 	str	x0, [x29, #48]
  400e84:	f9401fa0 	ldr	x0, [x29, #56]
  400e88:	f9400401 	ldr	x1, [x0, #8]
  400e8c:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400e90:	91096000 	add	x0, x0, #0x258
  400e94:	aa0103e2 	mov	x2, x1
  400e98:	f9401ba1 	ldr	x1, [x29, #48]
  400e9c:	97fffddd 	bl	400610 <printf@plt>
  400ea0:	f9401fa0 	ldr	x0, [x29, #56]
  400ea4:	f900041f 	str	xzr, [x0, #8]
  400ea8:	f9401fa0 	ldr	x0, [x29, #56]
  400eac:	f9400401 	ldr	x1, [x0, #8]
  400eb0:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400eb4:	9109e000 	add	x0, x0, #0x278
  400eb8:	97fffdd6 	bl	400610 <printf@plt>
  400ebc:	14000026 	b	400f54 <reverse_2+0x110>
  400ec0:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400ec4:	910a4000 	add	x0, x0, #0x290
  400ec8:	f9401ba1 	ldr	x1, [x29, #48]
  400ecc:	97fffdd1 	bl	400610 <printf@plt>
  400ed0:	f9401ba0 	ldr	x0, [x29, #48]
  400ed4:	f9400400 	ldr	x0, [x0, #8]
  400ed8:	f90017a0 	str	x0, [x29, #40]
  400edc:	f9401ba0 	ldr	x0, [x29, #48]
  400ee0:	f9400401 	ldr	x1, [x0, #8]
  400ee4:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400ee8:	910a8000 	add	x0, x0, #0x2a0
  400eec:	aa0103e2 	mov	x2, x1
  400ef0:	f94017a1 	ldr	x1, [x29, #40]
  400ef4:	97fffdc7 	bl	400610 <printf@plt>
  400ef8:	f9401ba0 	ldr	x0, [x29, #48]
  400efc:	f9401fa1 	ldr	x1, [x29, #56]
  400f00:	f9000401 	str	x1, [x0, #8]
  400f04:	f9401ba0 	ldr	x0, [x29, #48]
  400f08:	f9400401 	ldr	x1, [x0, #8]
  400f0c:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400f10:	910b0000 	add	x0, x0, #0x2c0
  400f14:	f9401fa2 	ldr	x2, [x29, #56]
  400f18:	97fffdbe 	bl	400610 <printf@plt>
  400f1c:	f9401ba0 	ldr	x0, [x29, #48]
  400f20:	f9001fa0 	str	x0, [x29, #56]
  400f24:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400f28:	910b8000 	add	x0, x0, #0x2e0
  400f2c:	f9401ba2 	ldr	x2, [x29, #48]
  400f30:	f9401fa1 	ldr	x1, [x29, #56]
  400f34:	97fffdb7 	bl	400610 <printf@plt>
  400f38:	f94017a0 	ldr	x0, [x29, #40]
  400f3c:	f9001ba0 	str	x0, [x29, #48]
  400f40:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400f44:	910be000 	add	x0, x0, #0x2f8
  400f48:	f94017a2 	ldr	x2, [x29, #40]
  400f4c:	f9401ba1 	ldr	x1, [x29, #48]
  400f50:	97fffdb0 	bl	400610 <printf@plt>
  400f54:	f9401ba0 	ldr	x0, [x29, #48]
  400f58:	f100001f 	cmp	x0, #0x0
  400f5c:	54fffb21 	b.ne	400ec0 <reverse_2+0x7c>  // b.any
  400f60:	f9400fa0 	ldr	x0, [x29, #24]
  400f64:	f9401fa1 	ldr	x1, [x29, #56]
  400f68:	f9000401 	str	x1, [x0, #8]
  400f6c:	f9400fa0 	ldr	x0, [x29, #24]
  400f70:	f9400401 	ldr	x1, [x0, #8]
  400f74:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400f78:	910c4000 	add	x0, x0, #0x310
  400f7c:	f9401fa2 	ldr	x2, [x29, #56]
  400f80:	97fffda4 	bl	400610 <printf@plt>
  400f84:	f9400fa0 	ldr	x0, [x29, #24]
  400f88:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400f8c:	d65f03c0 	ret

0000000000400f90 <merge_debug>:
  400f90:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400f94:	910003fd 	mov	x29, sp
  400f98:	f9000fa0 	str	x0, [x29, #24]
  400f9c:	f9000ba1 	str	x1, [x29, #16]
  400fa0:	f9400fa0 	ldr	x0, [x29, #24]
  400fa4:	f90017a0 	str	x0, [x29, #40]
  400fa8:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400fac:	910cc000 	add	x0, x0, #0x330
  400fb0:	f9400ba3 	ldr	x3, [x29, #16]
  400fb4:	f9400fa2 	ldr	x2, [x29, #24]
  400fb8:	f94017a1 	ldr	x1, [x29, #40]
  400fbc:	97fffd95 	bl	400610 <printf@plt>
  400fc0:	1400000f 	b	400ffc <merge_debug+0x6c>
  400fc4:	f94017a0 	ldr	x0, [x29, #40]
  400fc8:	f9400401 	ldr	x1, [x0, #8]
  400fcc:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400fd0:	910d4000 	add	x0, x0, #0x350
  400fd4:	aa0103e2 	mov	x2, x1
  400fd8:	f94017a1 	ldr	x1, [x29, #40]
  400fdc:	97fffd8d 	bl	400610 <printf@plt>
  400fe0:	f94017a0 	ldr	x0, [x29, #40]
  400fe4:	f9400400 	ldr	x0, [x0, #8]
  400fe8:	f90017a0 	str	x0, [x29, #40]
  400fec:	d0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  400ff0:	910dc000 	add	x0, x0, #0x370
  400ff4:	f94017a1 	ldr	x1, [x29, #40]
  400ff8:	97fffd86 	bl	400610 <printf@plt>
  400ffc:	f94017a0 	ldr	x0, [x29, #40]
  401000:	f9400400 	ldr	x0, [x0, #8]
  401004:	f100001f 	cmp	x0, #0x0
  401008:	54fffde1 	b.ne	400fc4 <merge_debug+0x34>  // b.any
  40100c:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  401010:	910e2000 	add	x0, x0, #0x388
  401014:	f94017a1 	ldr	x1, [x29, #40]
  401018:	97fffd7e 	bl	400610 <printf@plt>
  40101c:	f94017a0 	ldr	x0, [x29, #40]
  401020:	f9400ba1 	ldr	x1, [x29, #16]
  401024:	f9000401 	str	x1, [x0, #8]
  401028:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  40102c:	910e8000 	add	x0, x0, #0x3a0
  401030:	f9400fa2 	ldr	x2, [x29, #24]
  401034:	f94017a1 	ldr	x1, [x29, #40]
  401038:	97fffd76 	bl	400610 <printf@plt>
  40103c:	f9400fa0 	ldr	x0, [x29, #24]
  401040:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401044:	d65f03c0 	ret

0000000000401048 <init_list>:
  401048:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40104c:	910003fd 	mov	x29, sp
  401050:	f9000fa0 	str	x0, [x29, #24]
  401054:	d2800200 	mov	x0, #0x10                  	// #16
  401058:	97fffd56 	bl	4005b0 <malloc@plt>
  40105c:	aa0003e1 	mov	x1, x0
  401060:	f9400fa0 	ldr	x0, [x29, #24]
  401064:	f9000001 	str	x1, [x0]
  401068:	f9400fa0 	ldr	x0, [x29, #24]
  40106c:	f100001f 	cmp	x0, #0x0
  401070:	54000081 	b.ne	401080 <init_list+0x38>  // b.any
  401074:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  401078:	910ee000 	add	x0, x0, #0x3b8
  40107c:	97fffd5d 	bl	4005f0 <puts@plt>
  401080:	f9400fa0 	ldr	x0, [x29, #24]
  401084:	f9400000 	ldr	x0, [x0]
  401088:	b900001f 	str	wzr, [x0]
  40108c:	f9400fa0 	ldr	x0, [x29, #24]
  401090:	f9400000 	ldr	x0, [x0]
  401094:	f900041f 	str	xzr, [x0, #8]
  401098:	d503201f 	nop
  40109c:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4010a0:	d65f03c0 	ret

00000000004010a4 <length>:
  4010a4:	d10083ff 	sub	sp, sp, #0x20
  4010a8:	f90007e0 	str	x0, [sp, #8]
  4010ac:	f94007e0 	ldr	x0, [sp, #8]
  4010b0:	f9400000 	ldr	x0, [x0]
  4010b4:	f9000fe0 	str	x0, [sp, #24]
  4010b8:	14000007 	b	4010d4 <length+0x30>
  4010bc:	b94017e0 	ldr	w0, [sp, #20]
  4010c0:	11000400 	add	w0, w0, #0x1
  4010c4:	b90017e0 	str	w0, [sp, #20]
  4010c8:	f9400fe0 	ldr	x0, [sp, #24]
  4010cc:	f9400400 	ldr	x0, [x0, #8]
  4010d0:	f9000fe0 	str	x0, [sp, #24]
  4010d4:	f9400fe0 	ldr	x0, [sp, #24]
  4010d8:	f100001f 	cmp	x0, #0x0
  4010dc:	54ffff01 	b.ne	4010bc <length+0x18>  // b.any
  4010e0:	b94017e0 	ldr	w0, [sp, #20]
  4010e4:	910083ff 	add	sp, sp, #0x20
  4010e8:	d65f03c0 	ret

00000000004010ec <empty>:
  4010ec:	d10083ff 	sub	sp, sp, #0x20
  4010f0:	f90007e0 	str	x0, [sp, #8]
  4010f4:	f94007e0 	ldr	x0, [sp, #8]
  4010f8:	f9400000 	ldr	x0, [x0]
  4010fc:	f9000fe0 	str	x0, [sp, #24]
  401100:	f9400fe0 	ldr	x0, [sp, #24]
  401104:	f100001f 	cmp	x0, #0x0
  401108:	54000060 	b.eq	401114 <empty+0x28>  // b.none
  40110c:	52800020 	mov	w0, #0x1                   	// #1
  401110:	14000002 	b	401118 <empty+0x2c>
  401114:	52800000 	mov	w0, #0x0                   	// #0
  401118:	910083ff 	add	sp, sp, #0x20
  40111c:	d65f03c0 	ret

0000000000401120 <clean_list>:
  401120:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  401124:	910003fd 	mov	x29, sp
  401128:	f9000fa0 	str	x0, [x29, #24]
  40112c:	f9400fa0 	ldr	x0, [x29, #24]
  401130:	f9400000 	ldr	x0, [x0]
  401134:	f90017a0 	str	x0, [x29, #40]
  401138:	14000008 	b	401158 <clean_list+0x38>
  40113c:	f94017a0 	ldr	x0, [x29, #40]
  401140:	f9400400 	ldr	x0, [x0, #8]
  401144:	f90013a0 	str	x0, [x29, #32]
  401148:	f94017a0 	ldr	x0, [x29, #40]
  40114c:	97fffd2d 	bl	400600 <free@plt>
  401150:	f94013a0 	ldr	x0, [x29, #32]
  401154:	f90017a0 	str	x0, [x29, #40]
  401158:	f94017a0 	ldr	x0, [x29, #40]
  40115c:	f100001f 	cmp	x0, #0x0
  401160:	54fffee1 	b.ne	40113c <clean_list+0x1c>  // b.any
  401164:	d503201f 	nop
  401168:	a8c37bfd 	ldp	x29, x30, [sp], #48
  40116c:	d65f03c0 	ret

0000000000401170 <display>:
  401170:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  401174:	910003fd 	mov	x29, sp
  401178:	f9000fa0 	str	x0, [x29, #24]
  40117c:	f9400fa0 	ldr	x0, [x29, #24]
  401180:	f9400000 	ldr	x0, [x0]
  401184:	f90017a0 	str	x0, [x29, #40]
  401188:	14000009 	b	4011ac <display+0x3c>
  40118c:	f94017a0 	ldr	x0, [x29, #40]
  401190:	b9400001 	ldr	w1, [x0]
  401194:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  401198:	910f4000 	add	x0, x0, #0x3d0
  40119c:	97fffd1d 	bl	400610 <printf@plt>
  4011a0:	f94017a0 	ldr	x0, [x29, #40]
  4011a4:	f9400400 	ldr	x0, [x0, #8]
  4011a8:	f90017a0 	str	x0, [x29, #40]
  4011ac:	f94017a0 	ldr	x0, [x29, #40]
  4011b0:	f100001f 	cmp	x0, #0x0
  4011b4:	54fffec1 	b.ne	40118c <display+0x1c>  // b.any
  4011b8:	52800140 	mov	w0, #0xa                   	// #10
  4011bc:	97fffd19 	bl	400620 <putchar@plt>
  4011c0:	d503201f 	nop
  4011c4:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4011c8:	d65f03c0 	ret

00000000004011cc <putout>:
  4011cc:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4011d0:	910003fd 	mov	x29, sp
  4011d4:	f9000fa0 	str	x0, [x29, #24]
  4011d8:	f9400fa0 	ldr	x0, [x29, #24]
  4011dc:	f100001f 	cmp	x0, #0x0
  4011e0:	54000280 	b.eq	401230 <putout+0x64>  // b.none
  4011e4:	f9400fa0 	ldr	x0, [x29, #24]
  4011e8:	f9400400 	ldr	x0, [x0, #8]
  4011ec:	f90017a0 	str	x0, [x29, #40]
  4011f0:	14000009 	b	401214 <putout+0x48>
  4011f4:	f94017a0 	ldr	x0, [x29, #40]
  4011f8:	b9400001 	ldr	w1, [x0]
  4011fc:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  401200:	910f4000 	add	x0, x0, #0x3d0
  401204:	97fffd03 	bl	400610 <printf@plt>
  401208:	f94017a0 	ldr	x0, [x29, #40]
  40120c:	f9400400 	ldr	x0, [x0, #8]
  401210:	f90017a0 	str	x0, [x29, #40]
  401214:	f94017a0 	ldr	x0, [x29, #40]
  401218:	f100001f 	cmp	x0, #0x0
  40121c:	54fffec1 	b.ne	4011f4 <putout+0x28>  // b.any
  401220:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  401224:	910f6000 	add	x0, x0, #0x3d8
  401228:	97fffcf2 	bl	4005f0 <puts@plt>
  40122c:	14000002 	b	401234 <putout+0x68>
  401230:	d503201f 	nop
  401234:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401238:	d65f03c0 	ret

000000000040123c <insert_head>:
  40123c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  401240:	910003fd 	mov	x29, sp
  401244:	f9000fa0 	str	x0, [x29, #24]
  401248:	b90017a1 	str	w1, [x29, #20]
  40124c:	d2800200 	mov	x0, #0x10                  	// #16
  401250:	97fffcd8 	bl	4005b0 <malloc@plt>
  401254:	f90017a0 	str	x0, [x29, #40]
  401258:	f94017a0 	ldr	x0, [x29, #40]
  40125c:	f100001f 	cmp	x0, #0x0
  401260:	540000a1 	b.ne	401274 <insert_head+0x38>  // b.any
  401264:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  401268:	910f8000 	add	x0, x0, #0x3e0
  40126c:	97fffce1 	bl	4005f0 <puts@plt>
  401270:	1400000b 	b	40129c <insert_head+0x60>
  401274:	f94017a0 	ldr	x0, [x29, #40]
  401278:	b94017a1 	ldr	w1, [x29, #20]
  40127c:	b9000001 	str	w1, [x0]
  401280:	f9400fa0 	ldr	x0, [x29, #24]
  401284:	f9400001 	ldr	x1, [x0]
  401288:	f94017a0 	ldr	x0, [x29, #40]
  40128c:	f9000401 	str	x1, [x0, #8]
  401290:	f9400fa0 	ldr	x0, [x29, #24]
  401294:	f94017a1 	ldr	x1, [x29, #40]
  401298:	f9000001 	str	x1, [x0]
  40129c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4012a0:	d65f03c0 	ret

00000000004012a4 <insert_tail>:
  4012a4:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4012a8:	910003fd 	mov	x29, sp
  4012ac:	f9000fa0 	str	x0, [x29, #24]
  4012b0:	b90017a1 	str	w1, [x29, #20]
  4012b4:	d2800200 	mov	x0, #0x10                  	// #16
  4012b8:	97fffcbe 	bl	4005b0 <malloc@plt>
  4012bc:	f90013a0 	str	x0, [x29, #32]
  4012c0:	f94013a0 	ldr	x0, [x29, #32]
  4012c4:	f100001f 	cmp	x0, #0x0
  4012c8:	540000a1 	b.ne	4012dc <insert_tail+0x38>  // b.any
  4012cc:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  4012d0:	91100000 	add	x0, x0, #0x400
  4012d4:	97fffcc7 	bl	4005f0 <puts@plt>
  4012d8:	1400001b 	b	401344 <insert_tail+0xa0>
  4012dc:	f94013a0 	ldr	x0, [x29, #32]
  4012e0:	b94017a1 	ldr	w1, [x29, #20]
  4012e4:	b9000001 	str	w1, [x0]
  4012e8:	f94013a0 	ldr	x0, [x29, #32]
  4012ec:	f900041f 	str	xzr, [x0, #8]
  4012f0:	f9400fa0 	ldr	x0, [x29, #24]
  4012f4:	f9400000 	ldr	x0, [x0]
  4012f8:	f90017a0 	str	x0, [x29, #40]
  4012fc:	f9400fa0 	ldr	x0, [x29, #24]
  401300:	f9400000 	ldr	x0, [x0]
  401304:	f100001f 	cmp	x0, #0x0
  401308:	54000101 	b.ne	401328 <insert_tail+0x84>  // b.any
  40130c:	f9400fa0 	ldr	x0, [x29, #24]
  401310:	f94013a1 	ldr	x1, [x29, #32]
  401314:	f9000001 	str	x1, [x0]
  401318:	1400000b 	b	401344 <insert_tail+0xa0>
  40131c:	f94017a0 	ldr	x0, [x29, #40]
  401320:	f9400400 	ldr	x0, [x0, #8]
  401324:	f90017a0 	str	x0, [x29, #40]
  401328:	f94017a0 	ldr	x0, [x29, #40]
  40132c:	f9400400 	ldr	x0, [x0, #8]
  401330:	f100001f 	cmp	x0, #0x0
  401334:	54ffff41 	b.ne	40131c <insert_tail+0x78>  // b.any
  401338:	f94017a0 	ldr	x0, [x29, #40]
  40133c:	f94013a1 	ldr	x1, [x29, #32]
  401340:	f9000401 	str	x1, [x0, #8]
  401344:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401348:	d65f03c0 	ret

000000000040134c <insert_pos_head>:
  40134c:	a9bb7bfd 	stp	x29, x30, [sp, #-80]!
  401350:	910003fd 	mov	x29, sp
  401354:	f9000fa0 	str	x0, [x29, #24]
  401358:	b90017a1 	str	w1, [x29, #20]
  40135c:	b90013a2 	str	w2, [x29, #16]
  401360:	f9400fa0 	ldr	x0, [x29, #24]
  401364:	f9400000 	ldr	x0, [x0]
  401368:	f90027a0 	str	x0, [x29, #72]
  40136c:	f94027a0 	ldr	x0, [x29, #72]
  401370:	f100001f 	cmp	x0, #0x0
  401374:	54000061 	b.ne	401380 <insert_pos_head+0x34>  // b.any
  401378:	12800000 	mov	w0, #0xffffffff            	// #-1
  40137c:	14000038 	b	40145c <insert_pos_head+0x110>
  401380:	f9400fa0 	ldr	x0, [x29, #24]
  401384:	97ffff48 	bl	4010a4 <length>
  401388:	2a0003e1 	mov	w1, w0
  40138c:	b94013a0 	ldr	w0, [x29, #16]
  401390:	6b00003f 	cmp	w1, w0
  401394:	540000c2 	b.cs	4013ac <insert_pos_head+0x60>  // b.hs, b.nlast
  401398:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  40139c:	91108000 	add	x0, x0, #0x420
  4013a0:	97fffc94 	bl	4005f0 <puts@plt>
  4013a4:	12800000 	mov	w0, #0xffffffff            	// #-1
  4013a8:	1400002d 	b	40145c <insert_pos_head+0x110>
  4013ac:	d2800200 	mov	x0, #0x10                  	// #16
  4013b0:	97fffc80 	bl	4005b0 <malloc@plt>
  4013b4:	f9001fa0 	str	x0, [x29, #56]
  4013b8:	f9401fa0 	ldr	x0, [x29, #56]
  4013bc:	f100001f 	cmp	x0, #0x0
  4013c0:	540000c1 	b.ne	4013d8 <insert_pos_head+0x8c>  // b.any
  4013c4:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  4013c8:	9110e000 	add	x0, x0, #0x438
  4013cc:	97fffc89 	bl	4005f0 <puts@plt>
  4013d0:	12800000 	mov	w0, #0xffffffff            	// #-1
  4013d4:	14000022 	b	40145c <insert_pos_head+0x110>
  4013d8:	f9401fa0 	ldr	x0, [x29, #56]
  4013dc:	b94017a1 	ldr	w1, [x29, #20]
  4013e0:	b9000001 	str	w1, [x0]
  4013e4:	f9401fa0 	ldr	x0, [x29, #56]
  4013e8:	f900041f 	str	xzr, [x0, #8]
  4013ec:	b90047bf 	str	wzr, [x29, #68]
  4013f0:	14000017 	b	40144c <insert_pos_head+0x100>
  4013f4:	b94047a0 	ldr	w0, [x29, #68]
  4013f8:	11000400 	add	w0, w0, #0x1
  4013fc:	b90047a0 	str	w0, [x29, #68]
  401400:	f94027a0 	ldr	x0, [x29, #72]
  401404:	f9001ba0 	str	x0, [x29, #48]
  401408:	f94027a0 	ldr	x0, [x29, #72]
  40140c:	f9400400 	ldr	x0, [x0, #8]
  401410:	f90027a0 	str	x0, [x29, #72]
  401414:	f94027a0 	ldr	x0, [x29, #72]
  401418:	f90017a0 	str	x0, [x29, #40]
  40141c:	b94013a0 	ldr	w0, [x29, #16]
  401420:	51000400 	sub	w0, w0, #0x1
  401424:	b94047a1 	ldr	w1, [x29, #68]
  401428:	6b00003f 	cmp	w1, w0
  40142c:	54000101 	b.ne	40144c <insert_pos_head+0x100>  // b.any
  401430:	f9401ba0 	ldr	x0, [x29, #48]
  401434:	f9401fa1 	ldr	x1, [x29, #56]
  401438:	f9000401 	str	x1, [x0, #8]
  40143c:	f9401fa0 	ldr	x0, [x29, #56]
  401440:	f94017a1 	ldr	x1, [x29, #40]
  401444:	f9000401 	str	x1, [x0, #8]
  401448:	14000004 	b	401458 <insert_pos_head+0x10c>
  40144c:	f94027a0 	ldr	x0, [x29, #72]
  401450:	f100001f 	cmp	x0, #0x0
  401454:	54fffd01 	b.ne	4013f4 <insert_pos_head+0xa8>  // b.any
  401458:	52800000 	mov	w0, #0x0                   	// #0
  40145c:	a8c57bfd 	ldp	x29, x30, [sp], #80
  401460:	d65f03c0 	ret

0000000000401464 <insert_pos_tail>:
  401464:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  401468:	910003fd 	mov	x29, sp
  40146c:	f9000fa0 	str	x0, [x29, #24]
  401470:	b90017a1 	str	w1, [x29, #20]
  401474:	b90013a2 	str	w2, [x29, #16]
  401478:	f9400fa0 	ldr	x0, [x29, #24]
  40147c:	f9400000 	ldr	x0, [x0]
  401480:	f9001fa0 	str	x0, [x29, #56]
  401484:	f9401fa0 	ldr	x0, [x29, #56]
  401488:	f100001f 	cmp	x0, #0x0
  40148c:	54000061 	b.ne	401498 <insert_pos_tail+0x34>  // b.any
  401490:	12800000 	mov	w0, #0xffffffff            	// #-1
  401494:	14000037 	b	401570 <insert_pos_tail+0x10c>
  401498:	f9400fa0 	ldr	x0, [x29, #24]
  40149c:	97ffff02 	bl	4010a4 <length>
  4014a0:	2a0003e1 	mov	w1, w0
  4014a4:	b94013a0 	ldr	w0, [x29, #16]
  4014a8:	6b00003f 	cmp	w1, w0
  4014ac:	540000c2 	b.cs	4014c4 <insert_pos_tail+0x60>  // b.hs, b.nlast
  4014b0:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  4014b4:	91108000 	add	x0, x0, #0x420
  4014b8:	97fffc4e 	bl	4005f0 <puts@plt>
  4014bc:	12800000 	mov	w0, #0xffffffff            	// #-1
  4014c0:	1400002c 	b	401570 <insert_pos_tail+0x10c>
  4014c4:	d2800200 	mov	x0, #0x10                  	// #16
  4014c8:	97fffc3a 	bl	4005b0 <malloc@plt>
  4014cc:	f90017a0 	str	x0, [x29, #40]
  4014d0:	f94017a0 	ldr	x0, [x29, #40]
  4014d4:	f100001f 	cmp	x0, #0x0
  4014d8:	540000c1 	b.ne	4014f0 <insert_pos_tail+0x8c>  // b.any
  4014dc:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  4014e0:	9110e000 	add	x0, x0, #0x438
  4014e4:	97fffc43 	bl	4005f0 <puts@plt>
  4014e8:	12800000 	mov	w0, #0xffffffff            	// #-1
  4014ec:	14000021 	b	401570 <insert_pos_tail+0x10c>
  4014f0:	f94017a0 	ldr	x0, [x29, #40]
  4014f4:	b94017a1 	ldr	w1, [x29, #20]
  4014f8:	b9000001 	str	w1, [x0]
  4014fc:	f94017a0 	ldr	x0, [x29, #40]
  401500:	f900041f 	str	xzr, [x0, #8]
  401504:	b90037bf 	str	wzr, [x29, #52]
  401508:	14000016 	b	401560 <insert_pos_tail+0xfc>
  40150c:	b94037a0 	ldr	w0, [x29, #52]
  401510:	11000400 	add	w0, w0, #0x1
  401514:	b90037a0 	str	w0, [x29, #52]
  401518:	f9401fa0 	ldr	x0, [x29, #56]
  40151c:	f9400400 	ldr	x0, [x0, #8]
  401520:	f9001fa0 	str	x0, [x29, #56]
  401524:	f9401fa0 	ldr	x0, [x29, #56]
  401528:	f90013a0 	str	x0, [x29, #32]
  40152c:	b94013a0 	ldr	w0, [x29, #16]
  401530:	51000400 	sub	w0, w0, #0x1
  401534:	b94037a1 	ldr	w1, [x29, #52]
  401538:	6b00003f 	cmp	w1, w0
  40153c:	54000121 	b.ne	401560 <insert_pos_tail+0xfc>  // b.any
  401540:	f94013a0 	ldr	x0, [x29, #32]
  401544:	f9400401 	ldr	x1, [x0, #8]
  401548:	f94017a0 	ldr	x0, [x29, #40]
  40154c:	f9000401 	str	x1, [x0, #8]
  401550:	f94013a0 	ldr	x0, [x29, #32]
  401554:	f94017a1 	ldr	x1, [x29, #40]
  401558:	f9000401 	str	x1, [x0, #8]
  40155c:	14000004 	b	40156c <insert_pos_tail+0x108>
  401560:	f9401fa0 	ldr	x0, [x29, #56]
  401564:	f100001f 	cmp	x0, #0x0
  401568:	54fffd21 	b.ne	40150c <insert_pos_tail+0xa8>  // b.any
  40156c:	52800000 	mov	w0, #0x0                   	// #0
  401570:	a8c47bfd 	ldp	x29, x30, [sp], #64
  401574:	d65f03c0 	ret

0000000000401578 <delete_from_value>:
  401578:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  40157c:	910003fd 	mov	x29, sp
  401580:	f9000fa0 	str	x0, [x29, #24]
  401584:	b90017a1 	str	w1, [x29, #20]
  401588:	f9400fa0 	ldr	x0, [x29, #24]
  40158c:	f9400000 	ldr	x0, [x0]
  401590:	f90017a0 	str	x0, [x29, #40]
  401594:	f90013bf 	str	xzr, [x29, #32]
  401598:	1400000b 	b	4015c4 <delete_from_value+0x4c>
  40159c:	f94017a0 	ldr	x0, [x29, #40]
  4015a0:	b9400000 	ldr	w0, [x0]
  4015a4:	b94017a1 	ldr	w1, [x29, #20]
  4015a8:	6b00003f 	cmp	w1, w0
  4015ac:	54000140 	b.eq	4015d4 <delete_from_value+0x5c>  // b.none
  4015b0:	f94017a0 	ldr	x0, [x29, #40]
  4015b4:	f90013a0 	str	x0, [x29, #32]
  4015b8:	f94017a0 	ldr	x0, [x29, #40]
  4015bc:	f9400400 	ldr	x0, [x0, #8]
  4015c0:	f90017a0 	str	x0, [x29, #40]
  4015c4:	f94017a0 	ldr	x0, [x29, #40]
  4015c8:	f100001f 	cmp	x0, #0x0
  4015cc:	54fffe81 	b.ne	40159c <delete_from_value+0x24>  // b.any
  4015d0:	14000002 	b	4015d8 <delete_from_value+0x60>
  4015d4:	d503201f 	nop
  4015d8:	f94013a0 	ldr	x0, [x29, #32]
  4015dc:	f100001f 	cmp	x0, #0x0
  4015e0:	540000e1 	b.ne	4015fc <delete_from_value+0x84>  // b.any
  4015e4:	f9400fa0 	ldr	x0, [x29, #24]
  4015e8:	f9400000 	ldr	x0, [x0]
  4015ec:	f9400401 	ldr	x1, [x0, #8]
  4015f0:	f9400fa0 	ldr	x0, [x29, #24]
  4015f4:	f9000001 	str	x1, [x0]
  4015f8:	14000005 	b	40160c <delete_from_value+0x94>
  4015fc:	f94017a0 	ldr	x0, [x29, #40]
  401600:	f9400401 	ldr	x1, [x0, #8]
  401604:	f94013a0 	ldr	x0, [x29, #32]
  401608:	f9000401 	str	x1, [x0, #8]
  40160c:	f94017a0 	ldr	x0, [x29, #40]
  401610:	97fffbfc 	bl	400600 <free@plt>
  401614:	52800000 	mov	w0, #0x0                   	// #0
  401618:	a8c37bfd 	ldp	x29, x30, [sp], #48
  40161c:	d65f03c0 	ret

0000000000401620 <delete_position>:
  401620:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  401624:	910003fd 	mov	x29, sp
  401628:	f9000fa0 	str	x0, [x29, #24]
  40162c:	b90017a1 	str	w1, [x29, #20]
  401630:	f9400fa0 	ldr	x0, [x29, #24]
  401634:	f9400000 	ldr	x0, [x0]
  401638:	f9001fa0 	str	x0, [x29, #56]
  40163c:	f9401fa0 	ldr	x0, [x29, #56]
  401640:	f100001f 	cmp	x0, #0x0
  401644:	54000080 	b.eq	401654 <delete_position+0x34>  // b.none
  401648:	b94017a0 	ldr	w0, [x29, #20]
  40164c:	7100001f 	cmp	w0, #0x0
  401650:	540000ac 	b.gt	401664 <delete_position+0x44>
  401654:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  401658:	91118000 	add	x0, x0, #0x460
  40165c:	97fffbe5 	bl	4005f0 <puts@plt>
  401660:	1400002a 	b	401708 <delete_position+0xe8>
  401664:	b9002fbf 	str	wzr, [x29, #44]
  401668:	1400000d 	b	40169c <delete_position+0x7c>
  40166c:	b9402fa0 	ldr	w0, [x29, #44]
  401670:	11000400 	add	w0, w0, #0x1
  401674:	b9002fa0 	str	w0, [x29, #44]
  401678:	b9402fa1 	ldr	w1, [x29, #44]
  40167c:	b94017a0 	ldr	w0, [x29, #20]
  401680:	6b00003f 	cmp	w1, w0
  401684:	54000140 	b.eq	4016ac <delete_position+0x8c>  // b.none
  401688:	f9401fa0 	ldr	x0, [x29, #56]
  40168c:	f9001ba0 	str	x0, [x29, #48]
  401690:	f9401fa0 	ldr	x0, [x29, #56]
  401694:	f9400400 	ldr	x0, [x0, #8]
  401698:	f9001fa0 	str	x0, [x29, #56]
  40169c:	f9401fa0 	ldr	x0, [x29, #56]
  4016a0:	f100001f 	cmp	x0, #0x0
  4016a4:	54fffe41 	b.ne	40166c <delete_position+0x4c>  // b.any
  4016a8:	14000002 	b	4016b0 <delete_position+0x90>
  4016ac:	d503201f 	nop
  4016b0:	f9401fa0 	ldr	x0, [x29, #56]
  4016b4:	f100001f 	cmp	x0, #0x0
  4016b8:	540000a1 	b.ne	4016cc <delete_position+0xac>  // b.any
  4016bc:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  4016c0:	91122000 	add	x0, x0, #0x488
  4016c4:	97fffbcb 	bl	4005f0 <puts@plt>
  4016c8:	14000010 	b	401708 <delete_position+0xe8>
  4016cc:	b94017a0 	ldr	w0, [x29, #20]
  4016d0:	7100041f 	cmp	w0, #0x1
  4016d4:	540000e1 	b.ne	4016f0 <delete_position+0xd0>  // b.any
  4016d8:	f9400fa0 	ldr	x0, [x29, #24]
  4016dc:	f9400000 	ldr	x0, [x0]
  4016e0:	f9400401 	ldr	x1, [x0, #8]
  4016e4:	f9400fa0 	ldr	x0, [x29, #24]
  4016e8:	f9000001 	str	x1, [x0]
  4016ec:	14000005 	b	401700 <delete_position+0xe0>
  4016f0:	f9401fa0 	ldr	x0, [x29, #56]
  4016f4:	f9400401 	ldr	x1, [x0, #8]
  4016f8:	f9401ba0 	ldr	x0, [x29, #48]
  4016fc:	f9000401 	str	x1, [x0, #8]
  401700:	f9401fa0 	ldr	x0, [x29, #56]
  401704:	97fffbbf 	bl	400600 <free@plt>
  401708:	a8c47bfd 	ldp	x29, x30, [sp], #64
  40170c:	d65f03c0 	ret

0000000000401710 <delete_head>:
  401710:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  401714:	910003fd 	mov	x29, sp
  401718:	f9000fa0 	str	x0, [x29, #24]
  40171c:	f9400fa0 	ldr	x0, [x29, #24]
  401720:	f9400000 	ldr	x0, [x0]
  401724:	f90017a0 	str	x0, [x29, #40]
  401728:	f94017a0 	ldr	x0, [x29, #40]
  40172c:	f100001f 	cmp	x0, #0x0
  401730:	540000a1 	b.ne	401744 <delete_head+0x34>  // b.any
  401734:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  401738:	9112a000 	add	x0, x0, #0x4a8
  40173c:	97fffbad 	bl	4005f0 <puts@plt>
  401740:	14000008 	b	401760 <delete_head+0x50>
  401744:	f9400fa0 	ldr	x0, [x29, #24]
  401748:	f9400000 	ldr	x0, [x0]
  40174c:	f9400401 	ldr	x1, [x0, #8]
  401750:	f9400fa0 	ldr	x0, [x29, #24]
  401754:	f9000001 	str	x1, [x0]
  401758:	f94017a0 	ldr	x0, [x29, #40]
  40175c:	97fffba9 	bl	400600 <free@plt>
  401760:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401764:	d65f03c0 	ret

0000000000401768 <delete_tail>:
  401768:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  40176c:	910003fd 	mov	x29, sp
  401770:	f9000fa0 	str	x0, [x29, #24]
  401774:	f9400fa0 	ldr	x0, [x29, #24]
  401778:	f9400000 	ldr	x0, [x0]
  40177c:	f90017a0 	str	x0, [x29, #40]
  401780:	f90013bf 	str	xzr, [x29, #32]
  401784:	f94017a0 	ldr	x0, [x29, #40]
  401788:	f100001f 	cmp	x0, #0x0
  40178c:	54000141 	b.ne	4017b4 <delete_tail+0x4c>  // b.any
  401790:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  401794:	9112a000 	add	x0, x0, #0x4a8
  401798:	97fffb96 	bl	4005f0 <puts@plt>
  40179c:	14000014 	b	4017ec <delete_tail+0x84>
  4017a0:	f94017a0 	ldr	x0, [x29, #40]
  4017a4:	f90013a0 	str	x0, [x29, #32]
  4017a8:	f94017a0 	ldr	x0, [x29, #40]
  4017ac:	f9400400 	ldr	x0, [x0, #8]
  4017b0:	f90017a0 	str	x0, [x29, #40]
  4017b4:	f94017a0 	ldr	x0, [x29, #40]
  4017b8:	f9400400 	ldr	x0, [x0, #8]
  4017bc:	f100001f 	cmp	x0, #0x0
  4017c0:	54ffff01 	b.ne	4017a0 <delete_tail+0x38>  // b.any
  4017c4:	f94013a0 	ldr	x0, [x29, #32]
  4017c8:	f100001f 	cmp	x0, #0x0
  4017cc:	54000081 	b.ne	4017dc <delete_tail+0x74>  // b.any
  4017d0:	f9400fa0 	ldr	x0, [x29, #24]
  4017d4:	f900001f 	str	xzr, [x0]
  4017d8:	14000003 	b	4017e4 <delete_tail+0x7c>
  4017dc:	f94013a0 	ldr	x0, [x29, #32]
  4017e0:	f900041f 	str	xzr, [x0, #8]
  4017e4:	f94017a0 	ldr	x0, [x29, #40]
  4017e8:	97fffb86 	bl	400600 <free@plt>
  4017ec:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4017f0:	d65f03c0 	ret

00000000004017f4 <reverse>:
  4017f4:	d10083ff 	sub	sp, sp, #0x20
  4017f8:	f90007e0 	str	x0, [sp, #8]
  4017fc:	f94007e0 	ldr	x0, [sp, #8]
  401800:	f9400400 	ldr	x0, [x0, #8]
  401804:	f9000fe0 	str	x0, [sp, #24]
  401808:	f94007e0 	ldr	x0, [sp, #8]
  40180c:	f900041f 	str	xzr, [x0, #8]
  401810:	1400000d 	b	401844 <reverse+0x50>
  401814:	f9400fe0 	ldr	x0, [sp, #24]
  401818:	f9000be0 	str	x0, [sp, #16]
  40181c:	f9400fe0 	ldr	x0, [sp, #24]
  401820:	f9400400 	ldr	x0, [x0, #8]
  401824:	f9000fe0 	str	x0, [sp, #24]
  401828:	f94007e0 	ldr	x0, [sp, #8]
  40182c:	f9400401 	ldr	x1, [x0, #8]
  401830:	f9400be0 	ldr	x0, [sp, #16]
  401834:	f9000401 	str	x1, [x0, #8]
  401838:	f94007e0 	ldr	x0, [sp, #8]
  40183c:	f9400be1 	ldr	x1, [sp, #16]
  401840:	f9000401 	str	x1, [x0, #8]
  401844:	f9400fe0 	ldr	x0, [sp, #24]
  401848:	f100001f 	cmp	x0, #0x0
  40184c:	54fffe41 	b.ne	401814 <reverse+0x20>  // b.any
  401850:	d503201f 	nop
  401854:	910083ff 	add	sp, sp, #0x20
  401858:	d65f03c0 	ret

000000000040185c <reverse_perfect_return>:
  40185c:	d10083ff 	sub	sp, sp, #0x20
  401860:	f90007e0 	str	x0, [sp, #8]
  401864:	f94007e0 	ldr	x0, [sp, #8]
  401868:	f9000fe0 	str	x0, [sp, #24]
  40186c:	f90007ff 	str	xzr, [sp, #8]
  401870:	1400000b 	b	40189c <reverse_perfect_return+0x40>
  401874:	f9400fe0 	ldr	x0, [sp, #24]
  401878:	f9000be0 	str	x0, [sp, #16]
  40187c:	f9400fe0 	ldr	x0, [sp, #24]
  401880:	f9400400 	ldr	x0, [x0, #8]
  401884:	f9000fe0 	str	x0, [sp, #24]
  401888:	f9400be0 	ldr	x0, [sp, #16]
  40188c:	f94007e1 	ldr	x1, [sp, #8]
  401890:	f9000401 	str	x1, [x0, #8]
  401894:	f9400be0 	ldr	x0, [sp, #16]
  401898:	f90007e0 	str	x0, [sp, #8]
  40189c:	f9400fe0 	ldr	x0, [sp, #24]
  4018a0:	f100001f 	cmp	x0, #0x0
  4018a4:	54fffe81 	b.ne	401874 <reverse_perfect_return+0x18>  // b.any
  4018a8:	f94007e0 	ldr	x0, [sp, #8]
  4018ac:	910083ff 	add	sp, sp, #0x20
  4018b0:	d65f03c0 	ret

00000000004018b4 <reverse_perfect>:
  4018b4:	d10083ff 	sub	sp, sp, #0x20
  4018b8:	f90007e0 	str	x0, [sp, #8]
  4018bc:	f94007e0 	ldr	x0, [sp, #8]
  4018c0:	f9400000 	ldr	x0, [x0]
  4018c4:	f9000fe0 	str	x0, [sp, #24]
  4018c8:	f94007e0 	ldr	x0, [sp, #8]
  4018cc:	f900001f 	str	xzr, [x0]
  4018d0:	1400000d 	b	401904 <reverse_perfect+0x50>
  4018d4:	f9400fe0 	ldr	x0, [sp, #24]
  4018d8:	f9000be0 	str	x0, [sp, #16]
  4018dc:	f9400fe0 	ldr	x0, [sp, #24]
  4018e0:	f9400400 	ldr	x0, [x0, #8]
  4018e4:	f9000fe0 	str	x0, [sp, #24]
  4018e8:	f94007e0 	ldr	x0, [sp, #8]
  4018ec:	f9400001 	ldr	x1, [x0]
  4018f0:	f9400be0 	ldr	x0, [sp, #16]
  4018f4:	f9000401 	str	x1, [x0, #8]
  4018f8:	f94007e0 	ldr	x0, [sp, #8]
  4018fc:	f9400be1 	ldr	x1, [sp, #16]
  401900:	f9000001 	str	x1, [x0]
  401904:	f9400fe0 	ldr	x0, [sp, #24]
  401908:	f100001f 	cmp	x0, #0x0
  40190c:	54fffe41 	b.ne	4018d4 <reverse_perfect+0x20>  // b.any
  401910:	d503201f 	nop
  401914:	910083ff 	add	sp, sp, #0x20
  401918:	d65f03c0 	ret

000000000040191c <reverse_dis>:
  40191c:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  401920:	910003fd 	mov	x29, sp
  401924:	f9000fa0 	str	x0, [x29, #24]
  401928:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  40192c:	9112e000 	add	x0, x0, #0x4b8
  401930:	f9400fa1 	ldr	x1, [x29, #24]
  401934:	97fffb37 	bl	400610 <printf@plt>
  401938:	f9400fa0 	ldr	x0, [x29, #24]
  40193c:	f100001f 	cmp	x0, #0x0
  401940:	54000120 	b.eq	401964 <reverse_dis+0x48>  // b.none
  401944:	f9400fa0 	ldr	x0, [x29, #24]
  401948:	f9400400 	ldr	x0, [x0, #8]
  40194c:	97fffff4 	bl	40191c <reverse_dis>
  401950:	f9400fa0 	ldr	x0, [x29, #24]
  401954:	b9400001 	ldr	w1, [x0]
  401958:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  40195c:	91136000 	add	x0, x0, #0x4d8
  401960:	97fffb2c 	bl	400610 <printf@plt>
  401964:	52800140 	mov	w0, #0xa                   	// #10
  401968:	97fffb2e 	bl	400620 <putchar@plt>
  40196c:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  401970:	91138000 	add	x0, x0, #0x4e0
  401974:	f9400fa1 	ldr	x1, [x29, #24]
  401978:	97fffb26 	bl	400610 <printf@plt>
  40197c:	d503201f 	nop
  401980:	a8c27bfd 	ldp	x29, x30, [sp], #32
  401984:	d65f03c0 	ret

0000000000401988 <merge>:
  401988:	d10083ff 	sub	sp, sp, #0x20
  40198c:	f90007e0 	str	x0, [sp, #8]
  401990:	f90003e1 	str	x1, [sp]
  401994:	f94007e0 	ldr	x0, [sp, #8]
  401998:	f9000fe0 	str	x0, [sp, #24]
  40199c:	14000004 	b	4019ac <merge+0x24>
  4019a0:	f9400fe0 	ldr	x0, [sp, #24]
  4019a4:	f9400400 	ldr	x0, [x0, #8]
  4019a8:	f9000fe0 	str	x0, [sp, #24]
  4019ac:	f9400fe0 	ldr	x0, [sp, #24]
  4019b0:	f9400400 	ldr	x0, [x0, #8]
  4019b4:	f100001f 	cmp	x0, #0x0
  4019b8:	54ffff41 	b.ne	4019a0 <merge+0x18>  // b.any
  4019bc:	f9400fe0 	ldr	x0, [sp, #24]
  4019c0:	f94003e1 	ldr	x1, [sp]
  4019c4:	f9000401 	str	x1, [x0, #8]
  4019c8:	f94007e0 	ldr	x0, [sp, #8]
  4019cc:	910083ff 	add	sp, sp, #0x20
  4019d0:	d65f03c0 	ret

00000000004019d4 <merge_sort_recursion>:
  4019d4:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4019d8:	910003fd 	mov	x29, sp
  4019dc:	f9000fa0 	str	x0, [x29, #24]
  4019e0:	f9000ba1 	str	x1, [x29, #16]
  4019e4:	f9400fa0 	ldr	x0, [x29, #24]
  4019e8:	f100001f 	cmp	x0, #0x0
  4019ec:	54000061 	b.ne	4019f8 <merge_sort_recursion+0x24>  // b.any
  4019f0:	f9400ba0 	ldr	x0, [x29, #16]
  4019f4:	14000022 	b	401a7c <merge_sort_recursion+0xa8>
  4019f8:	f9400ba0 	ldr	x0, [x29, #16]
  4019fc:	f100001f 	cmp	x0, #0x0
  401a00:	54000061 	b.ne	401a0c <merge_sort_recursion+0x38>  // b.any
  401a04:	f9400fa0 	ldr	x0, [x29, #24]
  401a08:	1400001d 	b	401a7c <merge_sort_recursion+0xa8>
  401a0c:	f90017bf 	str	xzr, [x29, #40]
  401a10:	f9400fa0 	ldr	x0, [x29, #24]
  401a14:	b9400001 	ldr	w1, [x0]
  401a18:	f9400ba0 	ldr	x0, [x29, #16]
  401a1c:	b9400000 	ldr	w0, [x0]
  401a20:	6b00003f 	cmp	w1, w0
  401a24:	5400016a 	b.ge	401a50 <merge_sort_recursion+0x7c>  // b.tcont
  401a28:	f9400fa0 	ldr	x0, [x29, #24]
  401a2c:	f90017a0 	str	x0, [x29, #40]
  401a30:	f9400fa0 	ldr	x0, [x29, #24]
  401a34:	f9400400 	ldr	x0, [x0, #8]
  401a38:	f9400ba1 	ldr	x1, [x29, #16]
  401a3c:	97ffffe6 	bl	4019d4 <merge_sort_recursion>
  401a40:	aa0003e1 	mov	x1, x0
  401a44:	f94017a0 	ldr	x0, [x29, #40]
  401a48:	f9000401 	str	x1, [x0, #8]
  401a4c:	1400000b 	b	401a78 <merge_sort_recursion+0xa4>
  401a50:	f9400ba0 	ldr	x0, [x29, #16]
  401a54:	f90017a0 	str	x0, [x29, #40]
  401a58:	f9400ba0 	ldr	x0, [x29, #16]
  401a5c:	f9400400 	ldr	x0, [x0, #8]
  401a60:	aa0003e1 	mov	x1, x0
  401a64:	f9400fa0 	ldr	x0, [x29, #24]
  401a68:	97ffffdb 	bl	4019d4 <merge_sort_recursion>
  401a6c:	aa0003e1 	mov	x1, x0
  401a70:	f94017a0 	ldr	x0, [x29, #40]
  401a74:	f9000401 	str	x1, [x0, #8]
  401a78:	f94017a0 	ldr	x0, [x29, #40]
  401a7c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401a80:	d65f03c0 	ret

0000000000401a84 <merge_sort_>:
  401a84:	d100c3ff 	sub	sp, sp, #0x30
  401a88:	f90007e0 	str	x0, [sp, #8]
  401a8c:	f90003e1 	str	x1, [sp]
  401a90:	f94007e0 	ldr	x0, [sp, #8]
  401a94:	f9000be0 	str	x0, [sp, #16]
  401a98:	f94007e0 	ldr	x0, [sp, #8]
  401a9c:	f9000fe0 	str	x0, [sp, #24]
  401aa0:	f94007e0 	ldr	x0, [sp, #8]
  401aa4:	f90017e0 	str	x0, [sp, #40]
  401aa8:	f94003e0 	ldr	x0, [sp]
  401aac:	f90013e0 	str	x0, [sp, #32]
  401ab0:	14000027 	b	401b4c <merge_sort_+0xc8>
  401ab4:	f94017e1 	ldr	x1, [sp, #40]
  401ab8:	f94013e0 	ldr	x0, [sp, #32]
  401abc:	eb00003f 	cmp	x1, x0
  401ac0:	54000061 	b.ne	401acc <merge_sort_+0x48>  // b.any
  401ac4:	f90013ff 	str	xzr, [sp, #32]
  401ac8:	14000027 	b	401b64 <merge_sort_+0xe0>
  401acc:	f94017e0 	ldr	x0, [sp, #40]
  401ad0:	b9400001 	ldr	w1, [x0]
  401ad4:	f94013e0 	ldr	x0, [sp, #32]
  401ad8:	b9400000 	ldr	w0, [x0]
  401adc:	6b00003f 	cmp	w1, w0
  401ae0:	540001cd 	b.le	401b18 <merge_sort_+0x94>
  401ae4:	f9400fe0 	ldr	x0, [sp, #24]
  401ae8:	f94013e1 	ldr	x1, [sp, #32]
  401aec:	f9000401 	str	x1, [x0, #8]
  401af0:	f94013e0 	ldr	x0, [sp, #32]
  401af4:	f9400400 	ldr	x0, [x0, #8]
  401af8:	f90013e0 	str	x0, [sp, #32]
  401afc:	f9400fe0 	ldr	x0, [sp, #24]
  401b00:	f9400400 	ldr	x0, [x0, #8]
  401b04:	f9000fe0 	str	x0, [sp, #24]
  401b08:	f9400fe0 	ldr	x0, [sp, #24]
  401b0c:	f94017e1 	ldr	x1, [sp, #40]
  401b10:	f9000401 	str	x1, [x0, #8]
  401b14:	1400000e 	b	401b4c <merge_sort_+0xc8>
  401b18:	f94017e0 	ldr	x0, [sp, #40]
  401b1c:	f9400401 	ldr	x1, [x0, #8]
  401b20:	f94013e0 	ldr	x0, [sp, #32]
  401b24:	f9400400 	ldr	x0, [x0, #8]
  401b28:	eb00003f 	cmp	x1, x0
  401b2c:	54000061 	b.ne	401b38 <merge_sort_+0xb4>  // b.any
  401b30:	f94013e0 	ldr	x0, [sp, #32]
  401b34:	f900041f 	str	xzr, [x0, #8]
  401b38:	f94017e0 	ldr	x0, [sp, #40]
  401b3c:	f9000fe0 	str	x0, [sp, #24]
  401b40:	f94017e0 	ldr	x0, [sp, #40]
  401b44:	f9400400 	ldr	x0, [x0, #8]
  401b48:	f90017e0 	str	x0, [sp, #40]
  401b4c:	f94017e0 	ldr	x0, [sp, #40]
  401b50:	f100001f 	cmp	x0, #0x0
  401b54:	54000080 	b.eq	401b64 <merge_sort_+0xe0>  // b.none
  401b58:	f94013e0 	ldr	x0, [sp, #32]
  401b5c:	f100001f 	cmp	x0, #0x0
  401b60:	54fffaa1 	b.ne	401ab4 <merge_sort_+0x30>  // b.any
  401b64:	f94017e0 	ldr	x0, [sp, #40]
  401b68:	f100001f 	cmp	x0, #0x0
  401b6c:	54000060 	b.eq	401b78 <merge_sort_+0xf4>  // b.none
  401b70:	f94017e0 	ldr	x0, [sp, #40]
  401b74:	14000002 	b	401b7c <merge_sort_+0xf8>
  401b78:	f94013e0 	ldr	x0, [sp, #32]
  401b7c:	f9400fe1 	ldr	x1, [sp, #24]
  401b80:	f9000420 	str	x0, [x1, #8]
  401b84:	f9400be0 	ldr	x0, [sp, #16]
  401b88:	9100c3ff 	add	sp, sp, #0x30
  401b8c:	d65f03c0 	ret

0000000000401b90 <merge_sort>:
  401b90:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  401b94:	910003fd 	mov	x29, sp
  401b98:	f9000fa0 	str	x0, [x29, #24]
  401b9c:	f9000ba1 	str	x1, [x29, #16]
  401ba0:	f9400fa0 	ldr	x0, [x29, #24]
  401ba4:	f100001f 	cmp	x0, #0x0
  401ba8:	540000a0 	b.eq	401bbc <merge_sort+0x2c>  // b.none
  401bac:	f9400fa0 	ldr	x0, [x29, #24]
  401bb0:	f9400400 	ldr	x0, [x0, #8]
  401bb4:	f100001f 	cmp	x0, #0x0
  401bb8:	54000061 	b.ne	401bc4 <merge_sort+0x34>  // b.any
  401bbc:	f9400ba0 	ldr	x0, [x29, #16]
  401bc0:	14000065 	b	401d54 <merge_sort+0x1c4>
  401bc4:	f9400ba0 	ldr	x0, [x29, #16]
  401bc8:	f100001f 	cmp	x0, #0x0
  401bcc:	540000a0 	b.eq	401be0 <merge_sort+0x50>  // b.none
  401bd0:	f9400ba0 	ldr	x0, [x29, #16]
  401bd4:	f9400400 	ldr	x0, [x0, #8]
  401bd8:	f100001f 	cmp	x0, #0x0
  401bdc:	54000061 	b.ne	401be8 <merge_sort+0x58>  // b.any
  401be0:	f9400fa0 	ldr	x0, [x29, #24]
  401be4:	1400005c 	b	401d54 <merge_sort+0x1c4>
  401be8:	d2800200 	mov	x0, #0x10                  	// #16
  401bec:	97fffa71 	bl	4005b0 <malloc@plt>
  401bf0:	f90013a0 	str	x0, [x29, #32]
  401bf4:	f90017bf 	str	xzr, [x29, #40]
  401bf8:	f9400fa0 	ldr	x0, [x29, #24]
  401bfc:	f100001f 	cmp	x0, #0x0
  401c00:	540002e0 	b.eq	401c5c <merge_sort+0xcc>  // b.none
  401c04:	f9400ba0 	ldr	x0, [x29, #16]
  401c08:	f100001f 	cmp	x0, #0x0
  401c0c:	54000280 	b.eq	401c5c <merge_sort+0xcc>  // b.none
  401c10:	f9400fa0 	ldr	x0, [x29, #24]
  401c14:	b9400001 	ldr	w1, [x0]
  401c18:	f9400ba0 	ldr	x0, [x29, #16]
  401c1c:	b9400000 	ldr	w0, [x0]
  401c20:	6b00003f 	cmp	w1, w0
  401c24:	5400010c 	b.gt	401c44 <merge_sort+0xb4>
  401c28:	f94013a0 	ldr	x0, [x29, #32]
  401c2c:	f9400fa1 	ldr	x1, [x29, #24]
  401c30:	f9000401 	str	x1, [x0, #8]
  401c34:	f9400fa0 	ldr	x0, [x29, #24]
  401c38:	f9400400 	ldr	x0, [x0, #8]
  401c3c:	f9000fa0 	str	x0, [x29, #24]
  401c40:	14000007 	b	401c5c <merge_sort+0xcc>
  401c44:	f94013a0 	ldr	x0, [x29, #32]
  401c48:	f9400ba1 	ldr	x1, [x29, #16]
  401c4c:	f9000401 	str	x1, [x0, #8]
  401c50:	f9400ba0 	ldr	x0, [x29, #16]
  401c54:	f9400400 	ldr	x0, [x0, #8]
  401c58:	f9000ba0 	str	x0, [x29, #16]
  401c5c:	f94013a0 	ldr	x0, [x29, #32]
  401c60:	f9400400 	ldr	x0, [x0, #8]
  401c64:	f90017a0 	str	x0, [x29, #40]
  401c68:	1400001a 	b	401cd0 <merge_sort+0x140>
  401c6c:	f9400fa0 	ldr	x0, [x29, #24]
  401c70:	b9400001 	ldr	w1, [x0]
  401c74:	f9400ba0 	ldr	x0, [x29, #16]
  401c78:	b9400000 	ldr	w0, [x0]
  401c7c:	6b00003f 	cmp	w1, w0
  401c80:	5400016c 	b.gt	401cac <merge_sort+0x11c>
  401c84:	f94017a0 	ldr	x0, [x29, #40]
  401c88:	f9400fa1 	ldr	x1, [x29, #24]
  401c8c:	f9000401 	str	x1, [x0, #8]
  401c90:	f9400fa0 	ldr	x0, [x29, #24]
  401c94:	f9400400 	ldr	x0, [x0, #8]
  401c98:	f9000fa0 	str	x0, [x29, #24]
  401c9c:	f94017a0 	ldr	x0, [x29, #40]
  401ca0:	f9400400 	ldr	x0, [x0, #8]
  401ca4:	f90017a0 	str	x0, [x29, #40]
  401ca8:	1400000a 	b	401cd0 <merge_sort+0x140>
  401cac:	f94017a0 	ldr	x0, [x29, #40]
  401cb0:	f9400ba1 	ldr	x1, [x29, #16]
  401cb4:	f9000401 	str	x1, [x0, #8]
  401cb8:	f9400ba0 	ldr	x0, [x29, #16]
  401cbc:	f9400400 	ldr	x0, [x0, #8]
  401cc0:	f9000ba0 	str	x0, [x29, #16]
  401cc4:	f94017a0 	ldr	x0, [x29, #40]
  401cc8:	f9400400 	ldr	x0, [x0, #8]
  401ccc:	f90017a0 	str	x0, [x29, #40]
  401cd0:	f9400fa0 	ldr	x0, [x29, #24]
  401cd4:	f100001f 	cmp	x0, #0x0
  401cd8:	540001c0 	b.eq	401d10 <merge_sort+0x180>  // b.none
  401cdc:	f9400ba0 	ldr	x0, [x29, #16]
  401ce0:	f100001f 	cmp	x0, #0x0
  401ce4:	54fffc41 	b.ne	401c6c <merge_sort+0xdc>  // b.any
  401ce8:	1400000a 	b	401d10 <merge_sort+0x180>
  401cec:	f94017a0 	ldr	x0, [x29, #40]
  401cf0:	f9400fa1 	ldr	x1, [x29, #24]
  401cf4:	f9000401 	str	x1, [x0, #8]
  401cf8:	f9400fa0 	ldr	x0, [x29, #24]
  401cfc:	f9400400 	ldr	x0, [x0, #8]
  401d00:	f9000fa0 	str	x0, [x29, #24]
  401d04:	f94017a0 	ldr	x0, [x29, #40]
  401d08:	f9400400 	ldr	x0, [x0, #8]
  401d0c:	f90017a0 	str	x0, [x29, #40]
  401d10:	f9400fa0 	ldr	x0, [x29, #24]
  401d14:	f100001f 	cmp	x0, #0x0
  401d18:	54fffea1 	b.ne	401cec <merge_sort+0x15c>  // b.any
  401d1c:	1400000a 	b	401d44 <merge_sort+0x1b4>
  401d20:	f94017a0 	ldr	x0, [x29, #40]
  401d24:	f9400ba1 	ldr	x1, [x29, #16]
  401d28:	f9000401 	str	x1, [x0, #8]
  401d2c:	f9400ba0 	ldr	x0, [x29, #16]
  401d30:	f9400400 	ldr	x0, [x0, #8]
  401d34:	f9000ba0 	str	x0, [x29, #16]
  401d38:	f94017a0 	ldr	x0, [x29, #40]
  401d3c:	f9400400 	ldr	x0, [x0, #8]
  401d40:	f90017a0 	str	x0, [x29, #40]
  401d44:	f9400ba0 	ldr	x0, [x29, #16]
  401d48:	f100001f 	cmp	x0, #0x0
  401d4c:	54fffea1 	b.ne	401d20 <merge_sort+0x190>  // b.any
  401d50:	f94013a0 	ldr	x0, [x29, #32]
  401d54:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401d58:	d65f03c0 	ret

0000000000401d5c <main>:
  401d5c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  401d60:	910003fd 	mov	x29, sp
  401d64:	b0000000 	adrp	x0, 402000 <_IO_stdin_used+0x120>
  401d68:	91140000 	add	x0, x0, #0x500
  401d6c:	97fffa21 	bl	4005f0 <puts@plt>
  401d70:	f9000fbf 	str	xzr, [x29, #24]
  401d74:	f9400fa0 	ldr	x0, [x29, #24]
  401d78:	f90013a0 	str	x0, [x29, #32]
  401d7c:	910083a0 	add	x0, x29, #0x20
  401d80:	528007a1 	mov	w1, #0x3d                  	// #61
  401d84:	97fffd48 	bl	4012a4 <insert_tail>
  401d88:	910083a0 	add	x0, x29, #0x20
  401d8c:	52800901 	mov	w1, #0x48                  	// #72
  401d90:	97fffd45 	bl	4012a4 <insert_tail>
  401d94:	910083a0 	add	x0, x29, #0x20
  401d98:	528009c1 	mov	w1, #0x4e                  	// #78
  401d9c:	97fffd42 	bl	4012a4 <insert_tail>
  401da0:	910083a0 	add	x0, x29, #0x20
  401da4:	52800a81 	mov	w1, #0x54                  	// #84
  401da8:	97fffd3f 	bl	4012a4 <insert_tail>
  401dac:	910083a0 	add	x0, x29, #0x20
  401db0:	52800be1 	mov	w1, #0x5f                  	// #95
  401db4:	97fffd3c 	bl	4012a4 <insert_tail>
  401db8:	910083a0 	add	x0, x29, #0x20
  401dbc:	97fffced 	bl	401170 <display>
  401dc0:	910063a0 	add	x0, x29, #0x18
  401dc4:	528003e1 	mov	w1, #0x1f                  	// #31
  401dc8:	97fffd37 	bl	4012a4 <insert_tail>
  401dcc:	910063a0 	add	x0, x29, #0x18
  401dd0:	528052c1 	mov	w1, #0x296                 	// #662
  401dd4:	97fffd34 	bl	4012a4 <insert_tail>
  401dd8:	910063a0 	add	x0, x29, #0x18
  401ddc:	52800a61 	mov	w1, #0x53                  	// #83
  401de0:	97fffd31 	bl	4012a4 <insert_tail>
  401de4:	910063a0 	add	x0, x29, #0x18
  401de8:	52800bc1 	mov	w1, #0x5e                  	// #94
  401dec:	97fffd2e 	bl	4012a4 <insert_tail>
  401df0:	910063a0 	add	x0, x29, #0x18
  401df4:	52800d21 	mov	w1, #0x69                  	// #105
  401df8:	97fffd2b 	bl	4012a4 <insert_tail>
  401dfc:	910063a0 	add	x0, x29, #0x18
  401e00:	528000a1 	mov	w1, #0x5                   	// #5
  401e04:	97fffd28 	bl	4012a4 <insert_tail>
  401e08:	910063a0 	add	x0, x29, #0x18
  401e0c:	97fffcd9 	bl	401170 <display>
  401e10:	f94013a0 	ldr	x0, [x29, #32]
  401e14:	f9400fa1 	ldr	x1, [x29, #24]
  401e18:	97fffeef 	bl	4019d4 <merge_sort_recursion>
  401e1c:	f90017a0 	str	x0, [x29, #40]
  401e20:	9100a3a0 	add	x0, x29, #0x28
  401e24:	97fffcd3 	bl	401170 <display>
  401e28:	910083a0 	add	x0, x29, #0x20
  401e2c:	97fffcbd 	bl	401120 <clean_list>
  401e30:	910063a0 	add	x0, x29, #0x18
  401e34:	97fffcbb 	bl	401120 <clean_list>
  401e38:	52800000 	mov	w0, #0x0                   	// #0
  401e3c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401e40:	d65f03c0 	ret
  401e44:	00000000 	.inst	0x00000000 ; undefined

0000000000401e48 <__libc_csu_init>:
  401e48:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  401e4c:	910003fd 	mov	x29, sp
  401e50:	a901d7f4 	stp	x20, x21, [sp, #24]
  401e54:	b0000094 	adrp	x20, 412000 <__FRAME_END__+0xfad4>
  401e58:	b0000095 	adrp	x21, 412000 <__FRAME_END__+0xfad4>
  401e5c:	91374294 	add	x20, x20, #0xdd0
  401e60:	913722b5 	add	x21, x21, #0xdc8
  401e64:	a902dff6 	stp	x22, x23, [sp, #40]
  401e68:	cb150294 	sub	x20, x20, x21
  401e6c:	f9001ff8 	str	x24, [sp, #56]
  401e70:	2a0003f6 	mov	w22, w0
  401e74:	aa0103f7 	mov	x23, x1
  401e78:	9343fe94 	asr	x20, x20, #3
  401e7c:	aa0203f8 	mov	x24, x2
  401e80:	97fff9bc 	bl	400570 <_init>
  401e84:	b4000194 	cbz	x20, 401eb4 <__libc_csu_init+0x6c>
  401e88:	f9000bb3 	str	x19, [x29, #16]
  401e8c:	d2800013 	mov	x19, #0x0                   	// #0
  401e90:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  401e94:	aa1803e2 	mov	x2, x24
  401e98:	aa1703e1 	mov	x1, x23
  401e9c:	2a1603e0 	mov	w0, w22
  401ea0:	91000673 	add	x19, x19, #0x1
  401ea4:	d63f0060 	blr	x3
  401ea8:	eb13029f 	cmp	x20, x19
  401eac:	54ffff21 	b.ne	401e90 <__libc_csu_init+0x48>  // b.any
  401eb0:	f9400bb3 	ldr	x19, [x29, #16]
  401eb4:	a941d7f4 	ldp	x20, x21, [sp, #24]
  401eb8:	a942dff6 	ldp	x22, x23, [sp, #40]
  401ebc:	f9401ff8 	ldr	x24, [sp, #56]
  401ec0:	a8c47bfd 	ldp	x29, x30, [sp], #64
  401ec4:	d65f03c0 	ret

0000000000401ec8 <__libc_csu_fini>:
  401ec8:	d65f03c0 	ret

Disassembly of section .fini:

0000000000401ecc <_fini>:
  401ecc:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  401ed0:	910003fd 	mov	x29, sp
  401ed4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  401ed8:	d65f03c0 	ret
